libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;entity multiplier isport(
clk :instd_logic;
a :instd_logic_vector(31downto0);
b :instd_logic_vector(31downto0);
r :inoutstd_logic_vector(31downto0);
s :inoutstd_logic_vector(31downto0));end multiplier;architecture IMP of multiplier isbeginprocess(clk)beginif(clk'eventand clk = '1')then(r & s)<=(unsigned(a)*unsigned(b));endif;endprocess;end IMP;
i want to design a 32 bit multiplier and create multiplier ip. maximum bus size is 32 bit so can not use 64bit array for output: how to concatenate two 32 bit output arrays?
when i simulate above code error "Illegal target for assignment" is shown. pleas help me with this
VHDL doesn't know concatenations on the left-hand side of expression. Use an additional 64-bit wide signal or variable instead, assign respective parts of it to the port signals. In case of variable, assign under clock edge control, otherwise outside the process.