[Moved] Illegal target for assignment

[Akande]

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Code VHDL - [expand]
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
 
entity multiplier is
  port(
    clk : in std_logic;
    a   : in std_logic_vector(31 downto 0);
    b   : in std_logic_vector(31 downto 0);
    r   : inout std_logic_vector(31 downto 0);
    s     : inout std_logic_vector(31 downto 0)
     );
end multiplier;
 
 
architecture IMP of multiplier is
 
begin
  process (clk)
  begin
  
    if (clk'event and clk = '1') then
      (r & s)  <= (unsigned(a)* unsigned(b));
        end if;
  end process;
end IMP;

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i want to design a 32 bit multiplier and create multiplier ip. maximum bus size is 32 bit so can not use 64bit array for output: how to concatenate two 32 bit output arrays?
when i simulate above code error "Illegal target for assignment" is shown. pleas help me with this

 

[FvM]

VHDL doesn't know concatenations on the left-hand side of expression. Use an additional 64-bit wide signal or variable instead, assign respective parts of it to the port signals. In case of variable, assign under clock edge control, otherwise outside the process.

 

[TrickyDicky]

VHDL 2008 does allow it, but not in exactly that format:

(r,s) <= (unsigned(a)* unsigned(b));