[Moved] ERROR:Cpld:837 (xc9572xl) 72 macrocells

[Lokesh Waran]

While i am implementing the below verilog codings in CPLD -XC9572XL device the following error has been occurred .can anyone suggest me wat can we do for implement the same kind of various processes module codings (like phase locked loop,timer,automation purpose module) in single CPLD device, i know there is not enough space to fuse below coding due to less macrocell (72 macrocell) can any one suggest me which xilinx device is opt for this process either CPLD or FPGA ? I AM USING THIS FRO INDUSTRIAL AUTOMATION PURPOSE.THANK YOU

ERROR:Cpld:837 - Insufficient number of macrocells. The design needs at least 95
but only 72 left after allocating other resources.
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
the selected implementation options.

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Code Verilog - [expand]
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module pwm_cpld(clk,sw1,sw2,pulse,dc_out,a);
 
//input ports 
input clk;
input sw1,sw2;
 
//output ports
output pulse;
output dc_out;
output [3:0]a;
//............................................
//internal variables 
reg pulse ;
reg[12:0]cnt1=200;
reg[7:0]cnt=10;
reg[12:0]h;
reg[20:0]f;
 
always @(posedge clk)
   begin
      h<=h+1;
 
           if (h<cnt1)
                  pulse <=1'b1;
                  
                     else if ((h>cnt1) && (h < 2000))
                                  pulse <= 1'b0;
                          
                             else if (h>2000)
                                       h<=0;
                                          
   end 
             
always @ (posedge clk)
   begin 
   
           if (sw1==1'b0)
                begin
                   f<=f+1;
                        
                            if(f>1000000)
                                begin 
                                    cnt<=cnt+1;
                                     f  <=0; 
                                 end 
                                 
                                 if(cnt>=90)
                                     cnt<=90;
                    
    end         
//................................................................
 
if (sw2==1'b0)
    begin
           f<=f+1;
            
                  if (f>1000000) 
                       begin 
                          cnt<=cnt-1;
                            f  <= 0;
                        end
                    if (cnt<= 10)
                    
                          cnt<=10;
      end       
 
               cnt1<=cnt*20;
end
 
 
assign a =4'b0111;
assign dc_out =1'b0;
      
endmodule

---

 

[aruipksni]

While i am implementing the below verilog codings in CPLD -XC9572XL device the following error has been occurred .can anyone suggest me wat can we do for implement the same kind of various processes module codings (like phase locked loop,timer,automation purpose module) in single CPLD device, i know there is not enough space to fuse below coding due to less macrocell (72 macrocell) can any one suggest me which xilinx device is opt for this process either CPLD or FPGA ? I AM USING THIS FRO INDUSTRIAL AUTOMATION PURPOSE.THANK YOU

---

Code Verilog - [expand]
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module pwm_cpld(clk,sw1,sw2,pulse,dc_out,a);
 
//input ports 
input clk;
input sw1,sw2;
 
//output ports
output pulse;
output dc_out;
output [3:0]a;
//............................................
//internal variables 
reg pulse ;
reg[12:0]cnt1=200;
reg[7:0]cnt=10;
reg[12:0]h;
reg[20:0]f;
 
always @(posedge clk)
   begin
      h<=h+1;
 
           if (h<cnt1)
                  pulse <=1'b1;
                  
                     else if ((h>cnt1) && (h < 2000))
                                  pulse <= 1'b0;
                          
                             else if (h>2000)
                                       h<=0;
                                          
   end 
             
always @ (posedge clk)
   begin 
   
           if (sw1==1'b0)
                begin
                   f<=f+1;
                        
                            if(f>1000000)
                                begin 
                                    cnt<=cnt+1;
                                     f  <=0; 
                                 end 
                                 
                                 if(cnt>=90)
                                     cnt<=90;
                    
    end         
//................................................................
 
if (sw2==1'b0)
    begin
           f<=f+1;
            
                  if (f>1000000) 
                       begin 
                          cnt<=cnt-1;
                            f  <= 0;
                        end
                    if (cnt<= 10)
                    
                          cnt<=10;
      end       
 
               cnt1<=cnt*20;
end
 
 
assign a =4'b0111;
assign dc_out =1'b0;
      
endmodule

---

i guess it's the multiplection that takes a lot of logic.
are you sure you need to do it ?

 

[ads-ee]

aruipksni is correct the multiplication will require a lot of logic.

Besides the multiplication, you may end up with multiple compares to f with the value 1000000 with the following code.

  if (sw1==1'b0) begin
    f<=f+1;
    if (f>1000000) begin 
      cnt<=cnt+1;
      f  <=0; 
    end 
    if(cnt>=90)
      cnt<=90;
    end         
//................................................................
 
  if (sw2==1'b0) begin
    f<=f+1;
    if (f>1000000) begin 
      cnt<=cnt-1;
      f  <= 0;
    end
    if (cnt<= 10)
      cnt<=10;
    end       
    cnt1<=cnt*20;

I would check the synthesis results to see if the f > 1000000 is performed only once and a mux is used to assign the correct cnt+1 or cnt-1 to cnt.

I suggest combining these two if statements into one with sw1/2 used to mux the correct cnt values. This will also alleviate the issue with cnt probably having an indeterminate result due to the assignment of cnt in two different if statements based on the sw1 & sw2 values. If both sw1 & sw2 are 0 then what is cnt supposed to do?

In the following code do you want pulse to not update if h==2000?

  h<=h+1;
   if (h<cnt1)
    pulse <=1'b1;
  else if ((h>cnt1) && (h < 2000))
    pulse <= 1'b0;
  else if (h>2000)
    h<=0;

I also have problems with this style of coding as it implies that you want h to always increment, but suddenly in a priority encoded (with assignments to the unrelated output pulse) way you later have the comparison of h>2000 reset h to 0.
I think it is much clearer to have assignments to 1 output in an if statement unless all the outputs use the exact same set of if decisions.

Regards