Anyone that moved from VHDL to SystemVerilog, what advice do you have for others

[matrixofdynamism]

SystemVerilog has UVM and a lot of BFMs available. It can be the only language to use in certain highly complex projects where we want to use its many special features to create constrained random stimulus assertion based test benches.

Are there any users on this forum that moved from VHDL to SystemVerilog? How was your journey, please share with everyone.

 

[TrickyDicky]

Do you have a main reason for wanting to migrate? I have some experience with SV and UVM, and it really wasnt too much of a problem for me, but I have had previous experience with OO languages and VHDL verification training and experience so the work wasnt too daunting. But if your only VHDL experience is writing RTL and some basic testbenches, the move will be challenging. From my observations, SV/UVM has always been popular with ASIC, and it was gaining ground in FPGA, but the investment and training required to get up to speed with SV/UVM when you only know VHDL is massive. SV/UVM will NOT solve your verification problems for you and will NOT do the verification for you. This does seem to be a misunderstanding some people have about UVM. Verifcation requires the same investment in terms of specification and requirements that the design will need, maybe even more. And this would be for any verification language.

Its not so much the language thats the problem, but the whole new mindset. You are moving from RTL to OO programming, often with multiple threads running. Stuff will be "hidden" away from you.

A lot of the stuff you can do with SV/UVM can be done in pure VHDL. There are open source verification libraries now available in VHDL in the form of OSVVM (http://osvvm.org/ - written primarily by the chair of the VHDL standard comittee), uvvm (http://bitvis.no/dev-tools/uvvm/) and vunit (http://vunit.github.io/) . Each have a lot of the functionality you require (I think they all use the Randomisation from OSVVM) and will be more than enough for most tests.

For example, I have a Packet filter that routes packets to 2 destinations based on a set of about 12 different filter criteria. Using OSVVM, and some in house packet generation behavioural code, I can test all 12 packet criteria in a testbench that takes about 30s to compile and run from scratch. On each test run, the packets are randomly generated (constrained to fit the filter criteria) and provided in random orders, over an AXI bus that has random burst lengths. So each test run is unique (but still meets the requirements. This is a pure VHDL design and testbench.

I think the main reason that most people dont try VHDL for verification is they dont know what you can actually do with VHDL.

 

[dave_59]

Access to BFMs (or Verification IP VIP) is a key motivating factor. You have to weight the effort of creating VIP yourself versus the UVM learning curve.

Also, Constrained Random Stimulus generation is more than just generating random numbers. You have to know when a set of constraints is unsolvable and not waste time trying to keep guessing. And you have to identify the conflicting constraints. Only a formal constraint solver can do that for you. And you need functional coverage metrics to make sure your random stimulus is testing all your specific design requirements.

There were a number of papers from DVcon from people using VHDL adopting UVM. But the DVCon archives are still recovering from a database loss and are difficult to search at the moment.

SystemVerilog Primer for VHDL Engineers

This session teaches SystemVerilog using concepts from VHDL.

verificationacademy.com

 

[TrickyDicky]

Yes - BFMs are a key motivator - but UVVM, OSVVM and VUnit now all provide AXI BFMs, which I think covers a lot of the use cases in FPGAs. And they're free and open source.

Another issue is cost. IIRC, UVM often comes as an added cost to your simulation licensing, and BFMs can be a further cost. THe VHDL verification libraries are free and open source, with no extra costs in licencing required.