[moved] Do I need to model a big time in .lib ?

[tsuresh]

Hi,
Its related to .lib modelling of memory block.
I have two power down pins. These are asynchronous pins in nature.
________
A__/ \______________
_______________
B__/ \_______

There is a recovery window of 10us from falling edge of A to falling edge of B.

Question is : Does this needs to be modelled in .lib ?

If such huge timing is there, ecsmChecker tool throws an error saying that it has huge number ?
Does these kind of timings used during synthesis ? How does these timings used/non-used in STA ?

Could some one explain to me ?

 

[artmalik]

Re: Do I need to model a big time in .lib ?

Yeah you can model recovery window without any issue in the .lib. But these numbers are too big and I think these are generic numbers rather than hspice generated numbers. It makes more sense to do this checks in the Verilog RTL simulations with constraints in the Verilog models. You should add this constraint in the Verilog models rather than .lib.
ECSM checker is designed to check the timing numbers which have been simulated during characterization.

If you use this numbers in Verilog(where generally done) so all the problems mentioned above get solved.