I am synthesizing several digital designs with "design compiler" from synopsys, and after seeing the results of timing on critical paths, I am wondering if the tool is considering time margin to avoid future violations in the critical path?
Bottomline is there are margins everywhere, from spice to timing sign-off post fill database.
Gate level analysis is known not to be accurate enough. It is only an estimation of the actual delay that will appear after all gates are placed and routed. In this sense, yes, you can think of synthesis results as being margined.
Tool introduce timing margins provided by the user for modelling various behaviors which one could see in real silicon. At the DC stage we specify larger number for uncertainty to account these.We always provide the tight timing margins for the DC Tool to do a better job in optimizing the netlist.
Your silicon vendor will give you a fudge factor like 1.070458 and tell you to synthesis at a certain process corner with your nominal frequency times the fudge factor.
If you pass with 0 margin then it should work at all process corners,