[Moved:] [Cadence Virtuoso] Element value to be calculated on the fly

[adi_420]

Hi

I have a schematic in Cadence Virtuoso, where the output node has a pin 'out' connected to it. Now, I want to put the value of one resistance used in the same schematic in terms of 'out', say (1000*out) ohms. I want the resistance value to change during the course of simulation, taking 'out' value calculated in the previous step. Currently if I put this expression in object properties, I get a simulation error. Is there a way to do this, apart from modelling using Verilog?

Thanks.

 

[Dominik Przyborowski]

In ADE XL or Assembler you are able to make two different tests and to use value calculated from first test as variable in the second one.

 

[adi_420]

I am not aware of this method. Can you elaborate on it?

Thanks

 

[Dominik Przyborowski]

Look on this post

 

[dick_freebird]

Back when cdsSpice was the simulator, you used to have
print.N / read.N file I/O which I made heavy use of in,
for example, simulating laser-trimmed (post-fab) precision
analog parts across MC runs - one MC run (w/ looped trim
codes) to find the null code, print each, then another
MC run where trim code variables are read back and set
(no point in simulating Vio yield if you're not able to trim).

You're not going to find this in the GUI but you might
be able to do it in Ocean scripts. Ocean is a mess but
learning it may be good for you. I never got past the
simplest use (dump script and maybe add a loop or
something). But I think file I/O can probably be had,
define your data table format and read it like you wrote it.

 

[adi_420]

I looked into the post. It talks about running two separate tests. What I am looking for is running only one test, and and using the value calculated in the previous time step to be used for calculation of another value in the next time step. For example,
R(t)=2.1*V(t-1),
where both variables are part of the same test.
Any ideas for this?

 

[adi_420]

Ok. So you are suggesting that I scripting may be the only way out here. Do you have any idea if I can do this in Verilog-A?

 

[FvM]

I'm not specifically working with Cadence Virtuoso. A general property of circuit simulators is that they treat static component parameters (e.g. resistance values) and simulation variables (e.g. node voltages) differently. To make a controlled, e.g. a voltage dependent resistor, you need to refer to behavioral simulation statements that can represent arbitrary expressions combining simulation variables.

Review the Virtuoso manuals how behavior modeling can be implemented with this tool.

 

[dick_freebird]

Veriloga might be the way to go. But when you say R(t)
and V(t-1), I think about the difference between
simulation time and simulation timestep; are you going
to sample and set, or make this a continuous function,
and so on. Do you need to "remember", to react at a
fixed time lag, to continuously change with zero delay?
These are for you to think about. If you can express
it, I'm fairly optimistic that you can code it. But clarity
is a key stepping-stone, to that.