[Moved back]: How to determine tolerances for VT in a PVT in corner analysis?

[Fávero Santos]

Hello, all

Long story, short:
Someone told me I should use +- 10% in suply voltage and use -40 oC to 125 oC for temperature when running PVT corner analysis.

As I don't know how those magical numbers were determined, I would like to know how and why those values are used.

Thanks

 

[D.A.(Tony)Stewart]

Re: How to determine tolerances for VT in a PVT in corner analysis?

I used to run then manage DVT's and PVT's for hard disk drives for many years. It would consist with about 50 tests. 4 corner tests may include tempo, humidity and vibration.

First define your worst case environment, then the moderate stress level to accelerate process flaws to determine design /process margin and consider both Test to Failure and Test to pass/fail.

125'C from Arhennius Law for material degradation implies a rapid acceleration of failure rates often 2x per 10deg C rise above ambient of 25'C or 10 decades or 2^10th or 1000 x faster degradation rate and is often the max junction temp limit for semiconductors for reliable operation.

So it depends on your strategy and design specs. Look up HALT/HASS

 

[D.A.(Tony)Stewart]

Re: How to determine tolerances for VT in a PVT in corner analysis?

Is this for operating or non operating?
Component or system?
Design Spec limits?
All Hermetic sealed parts or not?

 

[erikl]

Re: How to determine tolerances for VT in a PVT in corner analysis?

Someone told me I should use +- 10% in suply voltage and use -40 oC to 125 oC for temperature when running PVT corner analysis.

+- 10% max. supply voltage variation is a standard for most semiconductor devices' specifications, see any dataSheet.

-55 °C to 125 °C is the ambient temperature range under so-called military specifications, s. dataSheets for semiconductor devices which are characterized with those specs.

 

[D.A.(Tony)Stewart]

Re: How to determine tolerances for VT in a PVT in corner analysis?

Although there are extended operating temperatures as for those who think -40'C is not cold enough for their application.. which might include Winnipeggers and space satellite systems.

Tspec Specification temperature range –40 85 °C
Ta = Operation temperature range . . –55 125 °C

Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits

TI

Been there... done that.... Tony.

 

[dick_freebird]

Re: [Moved]: How to determine tolerances for VT in a PVT in corner analysis?

The only place low temp is liable to affect reliability is
hot carrier type stuff.

For Process corners, you can look to the PCM/WAT
accept limits, call those +/-3 sigma (unless you know
better), take the UL-LL span and divide by 6 and there
is your gauss() sdev param (or, "goalpost" it using the
asserted process acceptance limits).

If you don't know what the foundry will throw your
way, analysis of this sort isn't going to have much basis.

 

[D.A.(Tony)Stewart]

Re: [Moved]: How to determine tolerances for VT in a PVT in corner analysis?

This is known as process capability. The ratio of deviation to designed limits. You may choose any higher number to ensure quality. The lower the worse control you have or the worse design you have. Either way Cpk is the metric to define the probability of escapes due to std deviation and design limits.

In order to extend any parameter beyond the test limits, you need to know how nonlinear the function is. e.g. diode voltage and CMOS transition time is very linear with 'C. But many processes are non-linear. Especially hydroscopic failures and freezing or thawing and condensation or particulate contamination in plasma etching resulting in ESD wounds during plasma etch.

https://en.wikipedia.org/wiki/Process_capability_index

It can be applied to any process or design limit.