I think this is a psychic test to discover who can read kvidhya's mind. Or maybe a hacking challenge to break into their computer...
If you want an answer kvidha, give us some clues as to which program and design you are talking about. It may be on the screen in front of you in India but my eyesight isn't good enough to see it from 8,000Km away!
Sure it makes sense. You just don't know anything about analog layout, Audioguru!
@kvidhya: Additional to betwixt's request, you should tell us where from your original layout file came (which tool, which PDK + version), and which DRC & LVS tool versions you are using. Rules' files could have changed.
"Some errors" is much less enlightening than transcribing
them. Most errors make an attempt to tell you what
they are about, in some fashion. You (OP) are not helping.
"Calling" the cell may mean you've placed it in some other
layout, perhaps to violate some other rules that have not
specifically to do with the intra-cell data in isolation.
the error which i got is due to connectivity
i raised this question because this type of errors i did not came across
generally connectivity problem gives an property error or net error
but i faced problem with the block which i faced some instantanious errors
but after rectify my small extension of metal
i solved my problem........