[moved] 2 stage CMOS OP-AMP design in Cadence

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sumovow

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I have designed an op-amp in Cadence with 45nm technology process file(gpdk045) as shown in the picture. VDD is provided 1V. But I am not getting desired output while transient analysis (both inverting and non-inverting mode). Can anyone please help me on this. Should I change any parameter or anything. It will be also helpful if anyone can suggest different type of Op-amp design. (in Cadence). Thank You
 

Did you adjust current less/more through NM0, until you obtain voltage changes at the node between PM0 & NM4 (the output of your differential amplifier)?
 

Show your test circuit incl. Vp, Vm connections and node voltages! What's your desired output?
 

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