MOSFET turn on Questions

[mirror_pole]

Hello guys,

I have some questions related to the attached diagramm. The diagramm represents the turn on process of a MOSFET with an inductive load.

1) T1-T2: After UGS reaches Vth, MOSFET starts to conduct. Why does VDS stay constant until T2? I assumed that as soon as the MOSFET starts to conduct, the VDS voltage starts to decrease. My only guess would be that since i have an inductive load, the change in Drain current induces a voltage of opposite direction. This effect keeps the drain voltage at the initial level, as long as the current is varrying with time. After T2 the current is constant, so the inductor is acting as a short and the drain voltage begins to decrease. Im not sure if my assumption is correct.

2) T2-T3: I understood that because of the miller effect, and therefore the big Cgd seeing from the input, the whole current provided to the Gate charges Cgd => VGS stays constant for that time. At the same time VDS is going down. Why does the current stay constant here? I thought that the current is dependent on VGS and VDS. Im assuming that i can refere to the standard equations for the drain current from the MOS Level 1 model. But im not sure if i can use this equations here.

3) I also dont quit understand the loading of the Cgd. In the initial state, when the MOSFET is off and there is no current, Cgd should be loaded to Vin right? Does the charging of Cgd already start from the begining? And why do i even have a plateau for VGS? Why does the whole current charges up Cgd and no charge to Cgs at some point?

4) What are the operating regions for the different time frames? I assumed that during T2-T3 im operating in the linear region, since VDS is decreasing and therefore rd (channel res) is decreasing. Do i operate in saturation region from T3 on?

 

[KlausST]

Hi,

1) it is an inductive load and no resistive load. This means you can treat it as constant current source.
You expect inductance current to be zero at the beginning. It represents the situation of an SMPS in CCM (continous conduction mode)
After t2 the current does increase, but too slow to be seen in this diagram. The diagram timing is in ns, but the current rises in the range of us.

2) Which current stays constant? The drain current --> see above.
The current is limited by the inductance (current) .... and there will be only a slow rise rate (relative to the diagram timing)
Again, see the inductance as constant current source for this situation.

3) you Say "there is no current" --> which current?
as the name says: C_GD. GD means Gate-to-drain. And this exactly is the voltage you have to watch.
C_GD will be charged when V_GS rises (parallel to C_GS). C_GD will also be charged when V_DS falls (miller) . With "charged" here I mean "currrent flow", i.e. relative change of charge and not the absolute state of charge.
During miller sitution V_GS stays constant, thus there is no currnet flow into C_GS, no change of charge in C_GS.

Klaus

 

[dick_freebird]

If ripple current is a small fraction of inductor current then across
cycles it will appear as a "fairly constant" current, at least that it
will persist roughly unchanged across the cycle. Its path to
complete the loop will change as the power stage state cycles,
though.

 

[mirror_pole]

Thank you guys for the answers. I still have some trouble to understand why i can see the inductance as a constant current source in this case.

About the Miller Plateau: Is it possible to think about it from a small signal perspective? When UGS reaches VTH the MOSFET will be immediately biased in saturation (since VDS>UGS-VTH). Lets assume that i have small signal gain of 10. That means that for a UGS change of lets say 1V i have -10V on the Drain. In this case the voltage across CGD will be larger then across CGS. This means that during the plateau CGD requires more charge, and thats why the current pushed into the gate from a driver is mainly flowing into the CGD capacitor (dQ=C*dU, UGS is rising by 1V, means dUGD=11V => dQ will be larger for CGD). At the End of the plateau, when VDS<UGS-VTH, the MOSFET goes into triode region. In triode the gain decreases and is 0 when VDS is 0. Now both capacitors CGS and CGD are beeing charged equally again, since we dont have the additional charge demand for CGD as previous in saturation.

 

[KlausST]

When UGS reaches VTH the MOSFET will be immediately biased in saturation (since VDS>UGS-VTH).

I´d say it´s rater the opposite.
During miller plateau V_DS moves from full voltage to close to zero.
Not saturated, fully linear operation mode.

And the current through the capacitor C_GD stays in balance with the gate drive current.
So V_GS moves just a bit, while V_DS moves maximal.

Klaus

 

[dick_freebird]

When you start talking about linear and saturation region
as if a power MOSFET is just a MOSFET, you are veering
off from understanding. A power MOSFET is a different
beast; out through the edge of the body implant it's a
MOSFET. But then comes the "neck" where planar MOS
surface conduction connects to the source of a body-
pinched JFET, effectively cascoding the MOSFET region.
The on resistance and lambda are dominated, or largely
determined by the neck and drift regions..

There's nothing about the Miller plateau which is small
signal. You might approximate some things with Cdg and
Rgg but you are in bang-bang world and plenty of that.
Add in that Cdg varies with Vds / Vdg (this is the neck
function, to push the drain field away from the fragile
gate as voltage increases, and this foot-race is key device
design).

 

[mirror_pole]

I´d say it´s rater the opposite.
During miller plateau V_DS moves from full voltage to close to zero.
Not saturated, fully linear operation mode.

And the current through the capacitor C_GD stays in balance with the gate drive current.
So V_GS moves just a bit, while V_DS moves maximal.

Klaus

This is actually what i meant. It starts at cut off, and moves directly to saturation. When the MOSFET is fully on it is in deep triode region with low rds(on).
About the inductor acting as a constant current source: I think i got it now, but just to make sure. Is it because the time constant RL is much bigger then the switching time of the MOSFET? In this case the current through the inductor only changes by a small amount during on/off switching of the MOSFET. Thats why i can approximate it as a constant current source.

 

[KlausST]

Constant current: exactly.

Klaus