Synchronous Buck control ICs need PNP turn off?

[cupoftea]

Hi,
The only way to use any offtheshelf Sync Buck controller is to use a PNP turn off on the low side FET.(as shown in attached LTspice and jpeg)
One needs to add a capacitor to the low side gate so that it doesnt get spuriously turned on by the upper fet turning on. When you have done that , you then must use a PNP turn off, otherwise you just cant turn the lo side gate off quickly enough. You can use a diode to bypass the gate series resistor, but with the logic level fets inevitably needed with these sync buck drivers, the voltage drop of the turn off diode is too high to be able to give a fast and definite turn off. As such, the PNP turn off is needed.

Why do they not show PNP turn off being used in the datasheets?

Another point is that the dead time between top and bottom fet drives is nowhere near long enough. (in any offtheshelf Buck IC) There is no need to have sub 100ns dead time...it just makes it more difficult to use gate delays to avoid shoot through.

Why do they all have such low dead time?

 

[D.A.(Tony)Stewart]

I'd like to challenge the assumptions that resulted in your questions with my answer below.

Also why 40s for simulation? I think all schematics should be 100% easily read with spacebar in LTspice. But I rarely use it.

 

[dick_freebird]

Maybe you are using FETs too fat for the controllers
you like, their output drive current. Over 1A starts to
be trouble for bond wires and very little upside to a
higher number - better to sell you a low output drive
controller and a plethora of MOSFET drivers.

 

[D.A.(Tony)Stewart]

Merry Xmas from Canada.

This mW boost regulator uses low C diodes so adding C to gate is worse than use RD gate filter but is not necessary for this low current.

Start surge current is absorbed by LR damping and Cin ESR.

If simulation does not match layout, add parasitic L or C to sim, to match, then understand shoot- thru error, then fix it. worst case deadtime just needs to be less than 1/2pi root(LC)

More import is to understand how to logically arrange schematic and evaluate where/why impulse currents are too big. e.g. positive feedback from gate pulse parasitic C to sense R input or L orientation into feedback loop.

--- Updated Dec 25, 2023 ---

When you reduce RdsOn, Ciss increases so for 1kW PS you may need BJT drivers to reduce Coss to drive high Ciss or change to SiC FETs.

 

[D.A.(Tony)Stewart]

Why do they all have such low dead time?

30 ns dead-time in my simulation while FET specs were perfect for that.

 

[D.A.(Tony)Stewart]

30 ns dead-time in my simulation while FET specs were perfect for that.
View attachment 187282

until they get hot then Td(off) and tf rises (runaway) so NG unless kept at room temp or well cooled.

Please learn from my schema logic and keep tighter placement with coil at right angles to Vfb and parts sensitive to flyback flux.