Mosfet Gate Drain Oxide

[ahsan_i_h]

hellow everybody,
why mosfet's gate drain oxide layer do not breakdown when Vgs=zero and Vds=maximum. According to the mosfet structure this is the same oxide layer which is between gate and source.
if anyone know this, please let me know.

 

[kemiyun]

The Mosfet actually should not have oxide layer over the source and drain region. However they have oxide region as a production flaw. The process guys design the gate oxide to withstand the defined supply voltage of the process. This is one of the reasons that the smaller technologies have lower supply voltages as their oxide is thin. Source side and drain side has no difference. Of course it will burn to death at some point . Actually the situation you asked happens in every digital cell. The thick oxide structure is used to withstand larger amounts of voltage at the drain side like in the LDMOS and some other asymmetrical transistors.

Is this what you asked for? Or am I missing something?

 

[ahsan_i_h]

The Mosfet actually should not have oxide layer over the source and drain region. However they have oxide region as a production flaw. The process guys design the gate oxide to withstand the defined supply voltage of the process. This is one of the reasons that the smaller technologies have lower supply voltages as their oxide is thin. Source side and drain side has no difference. Of course it will burn to death at some point . Actually the situation you asked happens in every digital cell. The thick oxide structure is used to withstand larger amounts of voltage at the drain side like in the LDMOS and some other asymmetrical transistors.

Is this what you asked for? Or am I missing something?

So the oxide layer between gate and body region is thin and the oxide layer between gate and drain region is thik. Is that right?

 

[kemiyun]

Well I can't say that it is done intentionally in a process for sure. I do not know much about that part. But considering that the area around the metal to poly contacts are oxide, at least this was the case for the technologies I am familiar with, the equivalent oxide thickness between the source and gate and, drain and gate will be larger. Therefore they can withstand higher voltage difference with respect to the gate.

Maybe you should look at the cells that are used for connecting input pins of the digital cells to ground or supply. They really use tricky ways to avoid connecting supply to the gate of a mosfet. However they have no such limitation for connecting it to source or drain.