Continue to Site

### Welcome to EDAboard.com

#### Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Status
Not open for further replies.

#### farhan89

##### Junior Member level 3
Hello,

I am simulating differential pair with resistive load and another with active load with differential output, I have read onlone and razavi book that Active load improves CMRR and also differential gain, but reason for this is not mentioned. can anyone guide me why we replace load resistors with MOS loads ? advantages /disadvantages?

Also I have a question that in resistive load I am measuring common mode gain at differential out, I have used this equation

is this equation correct for hand calculations ? If not which equation can I use for calculating common mode gain ?
Thanks!

1. Higher differential resistance than resistors (at the same voltage consumption) --> larger gain
2. Less silicon area consumption, less parasitic capacitance

The only disadvantage I can think of is (a little bit) more complexity. But resistors - too - usually have 3 terminals to be connected.

Also I have a question that in resistive load I am measuring common mode gain at differential out, I have used this equation

is this equation correct for hand calculations ?
The 1st part of the equation is correct and good enough for hand calculations.
For the 2nd part I'm missing the meaning of your abbreviated terms.

1. Higher differential resistance than resistors (at the same voltage consumption) --> larger gain
2. Less silicon area consumption, less parasitic capacitance

The only disadvantage I can think of is (a little bit) more complexity. But resistors - too - usually have 3 terminals to be connected.

The 1st part of the equation is correct and good enough for hand calculations.
For the 2nd part I'm missing the meaning of your abbreviated terms.

In equations the first part requires values that are not directly known, I need to analysi to calculate V_out,
in 2nd part,Δgm=gm1-gm2, Rd = load resistor , Rss is current source resistance. do you know any better equation to calculate common mode gain with resistive and MOS loads ?

in 2nd part,Δgm=gm1-gm2, Rd = load resistor , Rss is current source resistance. do you know any better equation to calculate common mode gain with resistive and MOS loads ?

No. I didn't even have this 2nd part ready in my head ;-)

The only disadvantage I can think of is (a little bit) more complexity. But resistors - too - usually have 3 terminals to be connected.

Two more reasons:

2. Resistor loaded diff pairs switch faster because of lower capacitance for a given resistance. CML logic is *usually* (but not always) done with passive loads.

2. Resistor loaded diff pairs switch faster because of lower capacitance for a given resistance. CML logic is *usually* (but not always) done with passive loads.

Here we are dealing with CMOS analog circuits. In this case, high-resistance resistors usually have essentially more parasitic capacitance than the corresponding transistors (much larger length). To create the same resistance (i.e. same gain) like a resistor, you need a much smaller transistor, because you make use of its differential resistance - even in the case of a MOS diode load (gate connected to drain).

Here we are dealing with CMOS analog circuits. In this case, high-resistance resistors usually have essentially more parasitic capacitance than the corresponding transistors (much larger length). To create the same resistance (i.e. same gain) like a resistor, you need a much smaller transistor, because you make use of its differential resistance - even in the case of a MOS diode load (gate connected to drain).

I disagree that a CML gate is not an analog circuit. To design on you need to worry about GBW, noise, swing, PSRR, gm, and the like. But depending on your definition, sure. You could think of it as a digital circuit designed by analog designers in an analog way.

I also disagree with you regarding the capacitance. I recently taped out a multi-Gb transmitter using CML gates in the transmit MUX. I did an extenstive design exploration and found the best GBW was had using diff pairs biased with the highest current density allowed (limited by electromigration) and passive loads. CML typically does not use large resistors. Therefore the transistors used to implement said resistors were not small (since resistance of a switch is inversely proportional to its W/L).

Don't take my word for it, though. In Michael Green's lectures on high-speed CMOS design at UC Irvine, he analyses the difference between passive and active loads. See slides 28-33.

Here are the slides: http://gram.eng.uci.edu/faculty/green/public/courses/270c/materials/lectures/Week4/Week4.pdf

surely you're right for RF circuits with hundreds of microAmps where you only need resistors in the kiloOhm range.

In contrast I was thinking of low-frequency low-noise input stages where you deal with currents in the order of a few microAmps, and therefore would need resistors in the range of several hundred kiloOhms. With available specific resistance values in the range of 1..10kΩ per square, the necessary resistors would consume a huge area - and provide corresponding parasitic capacitance.

Erik,

I see your point and agree. The original post was asking about op amp inputs and in that case, active loads are the way to go unless you want the absolute lowest noise possible and you are willing to make significant compromises to get it.

Indeed, the CML gates I was referring to had bias currents of several hundred microamps and load resistors of around 1 kOhm.

Status
Not open for further replies.