theguardian2001
Junior Member level 3

Hi, everyone!
I am currently doing a research on existing fully-differential typologies for fully-differential SAR ADCs to utilize some of these methodologies in my design. I have come up with a question and I would appreciate any reasonable comments and help.
The topology I am starting with looks like this one. In order to reduce the overall capacitance one places a coupling cap(s), which makes it easier for an input buffer to drive such a heavy load for high resolution.

However, there is one article people at the forum had discussed couple of times before written by Promitzer. The proposed design utilizes a resistive subDAC in order to provide a reference voltage to the bottom plate of the rightmost cap in the figure (the detailed figure shows the bottom part of a capacitive array corresponding to node VNB in the top-level schematic).


It is relatively straightforward that switching bottom plate of this cap to the nodes where an input voltage to be converted lies in, can be referred to using a subDAC which determines MSBs in that case with fully-differential topology. I was wondering if there exists a possibility to realize this voltage by using another type of subDAC, like current scaling or even the same type charge scaling capacitive one but with a lower resolution? Maybe somebody can refer me to a work utilizing such an approach. It would also like to explore the drawbacks of usage of the coupling capacitor I have mentioned in the beginning. Right now it seems like it relaxes driving capabilities for the input buffer (or S/H amplifier) and can at worse introduce some constant offset error, which can often be tolerated. Maybe someone can think of other disadvantages or challenges related to it.
Thanks everyone for help in advance.
I am currently doing a research on existing fully-differential typologies for fully-differential SAR ADCs to utilize some of these methodologies in my design. I have come up with a question and I would appreciate any reasonable comments and help.
The topology I am starting with looks like this one. In order to reduce the overall capacitance one places a coupling cap(s), which makes it easier for an input buffer to drive such a heavy load for high resolution.

However, there is one article people at the forum had discussed couple of times before written by Promitzer. The proposed design utilizes a resistive subDAC in order to provide a reference voltage to the bottom plate of the rightmost cap in the figure (the detailed figure shows the bottom part of a capacitive array corresponding to node VNB in the top-level schematic).


It is relatively straightforward that switching bottom plate of this cap to the nodes where an input voltage to be converted lies in, can be referred to using a subDAC which determines MSBs in that case with fully-differential topology. I was wondering if there exists a possibility to realize this voltage by using another type of subDAC, like current scaling or even the same type charge scaling capacitive one but with a lower resolution? Maybe somebody can refer me to a work utilizing such an approach. It would also like to explore the drawbacks of usage of the coupling capacitor I have mentioned in the beginning. Right now it seems like it relaxes driving capabilities for the input buffer (or S/H amplifier) and can at worse introduce some constant offset error, which can often be tolerated. Maybe someone can think of other disadvantages or challenges related to it.
Thanks everyone for help in advance.