subDAC vs coupling cap in fully-differential SAR ADC

[theguardian2001]

Hi, everyone!
I am currently doing a research on existing fully-differential typologies for fully-differential SAR ADCs to utilize some of these methodologies in my design. I have come up with a question and I would appreciate any reasonable comments and help.
The topology I am starting with looks like this one. In order to reduce the overall capacitance one places a coupling cap(s), which makes it easier for an input buffer to drive such a heavy load for high resolution.


However, there is one article people at the forum had discussed couple of times before written by Promitzer. The proposed design utilizes a resistive subDAC in order to provide a reference voltage to the bottom plate of the rightmost cap in the figure (the detailed figure shows the bottom part of a capacitive array corresponding to node VNB in the top-level schematic).

It is relatively straightforward that switching bottom plate of this cap to the nodes where an input voltage to be converted lies in, can be referred to using a subDAC which determines MSBs in that case with fully-differential topology. I was wondering if there exists a possibility to realize this voltage by using another type of subDAC, like current scaling or even the same type charge scaling capacitive one but with a lower resolution? Maybe somebody can refer me to a work utilizing such an approach. It would also like to explore the drawbacks of usage of the coupling capacitor I have mentioned in the beginning. Right now it seems like it relaxes driving capabilities for the input buffer (or S/H amplifier) and can at worse introduce some constant offset error, which can often be tolerated. Maybe someone can think of other disadvantages or challenges related to it.
Thanks everyone for help in advance.

 

[sidun.av]

Hi @theguardian2001 ,
It would be great if you can share the source article and Promitzer's discussion so we can have a better understanding of what you are talking about.

Also, why do you want to replace the subDAC with the lower resolution one? In terms of architecture of the subDAC, I think that current-steering DAC should be able to do the job as well, as soon as it has sufficient BW and current capacity.

Talking about decoupling capacitor drawbacks:
- It might increase the area and complexity of the layout (even though it is implemented using unity-weighted caps) creating more routing parasitics and hence causing nonlinearity;
- It might cause increased kT/C noise, but I am not sure.

 

[theguardian2001]

Thank you, sidun.av, for your fast reply.
I would share a thread on the forum where I firstly saw the link to the paper, since links to external resources are depicted somewhat strange on the forum and have a tendency to disappear with time. https://www.edaboard.com/threads/need-help-with-12-bit-sar-adc-design.66695/
The paper itself can be accessed/ searched as
G. Promitzer, "12-bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1 MS/s," in IEEE Journal of Solid-State Circuits, vol. 36, no. 7, pp. 1138-1143, July 2001, doi: 10.1109/4.933473.
keywords: {Capacitors;Switching circuits;Voltage;Energy consumption;Sampling methods;Capacitance;Clocks;Control systems;Logic;System-on-a-chip},

I was also thinking about current-scaling subDAC, but I am facing a difficulty to understand a functionality of such a circuit in terms of comparison phase. Let me explain what I mean by that. In a conventional single-ended SAR ADC we would generate a binary code, fed it then into a DAC and compare it with a sampled value of the input signal. It it pretty easy to imagine/understand how a subDAC with the resolution lower than a final number of bits can be realized. In terms of our theoretical discussion let's say that overall system its' resolution is 4 bits and after generating a code 1000 in register we apply two MSBs into, let's keep it simple, a voltage scaling subDAC as the one seen below to illustrate it clearly.

It is also clear, in this single-ended implementation, that voltage shown as Vo in the figure above will be used as Vref for a charge scaling DAC as the one seen in my previous message. And the result of the scaling with this Vo used as Vref for charge-scaling DAC is then compared to sampled Vin.

However, the switching schemes I have seen so far for fully-differential charge-scaling SAR ADC typologies relies not on generating a binary code and then converting it back to voltage, but rather then subtracting the fraction of Vref from differential input signal Vin+ - Vin-.

Here is where my confusion arises. In a single-ended SAR ADC, we generate a binary code and feed it to a DAC—which sets up a fixed reference voltage (Vo) for the subsequent charge scaling—making the conversion straightforward. For fully-differential charge-scaling SAR ADCs, however, the approach appears to differ. Rather than converting the binary code back into a fixed voltage, these architectures subtract a fraction of the reference voltage directly from the differential input signal (Vin⁺–Vin⁻).

My initial thought was to mirror the single-ended concept: using the most significant bits resolved by a sub-DAC to generate a reference (let’s call it Vref_new) that would now drive the charge-scaling. However, since this fully-differential approach does not inherently produce a binary code, I cannot see how to form Vref_new directly from the MSBs. The only solution I seem to have is to employ a sub-ADC—rather than another sub-DAC—to provide a rough estimate of the range of Vin⁺–Vin⁻, which could then define Vref_new.

Is this reasoning correct, or am I missing an alternative method to generate Vref_new within a fully-differential architecture?

That is nice that you have mentioned kT/C noise - as far as I understand it arises from the actual capacitance on the nodes where Vin+ and Vin- are sampled on. In that
case since the capacitance is reduced at least by the factor of two with a single coupling cap - KT/C noise would increase. But is that actually stays true in that very case?