Mos with high k dielectric HfO2

[mujahed]

Mos with high k dielectric gate oxide HfO2

Hi
The oxide layer of MOS has been made of Hafnium Dioxide (HfO2) and has been grown using dry etching, in which during etching a thin layer of SiO2 will be formed as an intermediate layer between body and oxide. The thickness of SiO2 is 1 nm whereas the oxide thickness, in which is varied between 2 to 5 nm, has to be investigated using SILVACO.
The device has to be fabricated based-on 22 nm technology.

The aspect ratio (W/L) of the device is varied between 1.5 to 3.0 due to minimization of the overall design.

The thicknesses of “S” and “D” region as well as Silicide/Hafnide metals are arbitrary (not more than 100 nm) and whole device has to be fabricated on a single 450nm Si wafer.

Remember: Gate metal, Hf+Al, differs with “S”, “D”, and “B” that are Si+Al.

The doping concentrations of “S” and “D” region are either n+ or p+, depends on the bulk, must be done using Boron or Phosphor Ion-Implantation

1: C-V Analysis of Structure. Bulk: n-Si (1.5x1017 #/cm-3)
2: C-V Analysis of Structure. Bulk: p-Si (15x1017 #/cm-3)

Conclusion should address which feature (W/L) gives the best performance of the device in term of quantized electron density and either C-V or I-V characterization of the device

Can someone help me for silvaco code?

 

[mujahed]

Re: Mos with high k dielectric gate oxide HfO2

please help me
I'm new in silvaco

 

[Colbhaidh]

Search for Silvaco examples using HFO2. These are a good starting point.
e.g.
h**p://www.silvaco.com/examples/tcad/section24/example2/highkex02.in.html?keepThis=true&TB_iframe=true&height=500&width=760

 

[mujahed]

thanak you
But this is in atlas and the mos example of silvaco is in athena?

 

[Colbhaidh]

region num=1 y.min=0 y.max=1 silicon
region num=2 y.max=0 y.max=-0.002 material=oxide #2nm SiO2
region num=3 y.max=-0.002 y.min=-0.037 material=hf02 #35nm HfO2

Note: I do not have access to Silvaco that has HfO2 as a material, so I do not think I can be much help

 

[mujahed]

You've helped me a lot

 

[mujahed]

Hi
this is my code it seem's correct,doesn't it?
but i can not define electrode and body metal
please see this code and correct it if you need
I'm waiting for you...

#PMOS
#Bulk: n-Si (1.5x1017 #/cm3)


go athena
#
# Set up a mesh suitable for a single MOSFET device....
#
line x loc=0.0 spac=0.001
line x loc=0.2 spac=0.005
line x loc=0.225 spac=0.01
#
line y loc=0.0 spac=0.001 
line y loc=0.01 spac=0.001
line y loc=0.1 spac=0.05
line y loc=0.35 spac=0.1

# Start off by defining silicon with 1.5e17 phos doping...
# Decrease the folowing space.mult parameter for a denser
# mesh and more accuracy...
init orientation=100 c.phos=1.5e17 space.mult=1
# 
#epitaxy time=10 temp=800 thickness=0.3 divisions=15 dy=0.10 ydy=0.00 c.phos=1.50e17


#pwell formation including masking off of the nwell
#
diffus time=30 temp=1000 dryo2 press=1.00 hcl=3
#
etch oxide thick=0.039

#N-well Implant
implant amorphous phos dose=8e11 energy=100 pears
#
diffus temp=950 time=10 weto2 hcl=3
#
#N-well implant amorphous not shown -
#
# welldrive 
diffus time=20 temp=1200 nitro press=1
#
etch oxide all
#
#sacrificial "cleaning" oxide
diffus time=20 temp=1000 dryo2 press=1 hcl=3
#
etch oxide all




#gate oxide grown here:-

depo oxide thick=0.001
depo material=HfO2 thick=0.004 div=3 

# Extract a design parameter.....
extract name="gateox" thickness oxide mat.occno=1 x.val=0.005

depo material=Hf+Al thick=0.04
deposit photores thickness=0.01 div=3


etch photores p1.x=0.214 left
etch material=Hf+Al p1.x=0.214 left
etch material=HfO2 left p1.x=0.214
etch oxide p1.x=0.214 left


implant boron dose=1e18 energy=2

etch photores all

diffuse time=0.01 temp=1000

depo oxide thick=0.001
deposit material=Si+Al thickness=0.045 div=8

etch material=Si+Al thickness=0.045 right p1.x=0.150
etch material=Si+Al thickness=0.045 left p1.x=0.050


# Extract design parameters

# extract final S/D Xj
extract name="nxj" xj silicon mat.occno=1 x.val=0.1 junc.occno=1

# extract the N++ regions sheet resistance
extract name="n++ sheet rho" sheet.res material="Silicon" mat.occno=1 x.val=0.05 region.occno=1

# extract the sheet rho under the spacer, of the LDD region
extract name="ldd sheet rho" sheet.res material="Silicon" \
	mat.occno=1 x.val=0.3 region.occno=1

# extract the surface conc under the channel.
extract name="chan surf conc" surf.conc impurity="Net Doping" \
	material="Silicon" mat.occno=1 x.val=0.45

# extract a curve of conductance versus bias.
#extract start material="Polysilicon" mat.occno=1 \
#	bias=0.0 bias.step=0.2 bias.stop=2 x.val=0.45
extract done name="sheet cond v bias" \
	curve(bias,1dn.conduct material="Silicon" mat.occno=1  region.occno=1)\
	outfile="extract.dat"

# extract the long chan Vt
extract name="n1dvt" 1dvt ntype vb=0.0 qss=1e10 x.val=0.49






# mirror the structure.....
structure mirror right

# Name the electrodes...








# output the structure
structure outfile=devicepnp0.str 

# plot it
tonyplot  devicepnp0.str -set  device.set


############# PVt Test : Returns PVt, PBeta and PTheta ################
go atlas

# set material models
models cvt srh print  
contact name=gate highk.al on.HfO2
interface qf=3e10

# get initial solution
solve init


method  newton trap
solve prev

# Bias the drain a bit...
solve vdrain=-0.1 name=drain

# Ramp the gate
log outf=devicepnp1.log master
#solve vgate=0 vstep=-0.25 vfinal=-3.0 vdrain=-3.3 name=gate
SOLVE VGATE=0.0 NAME=GATE vstep=-0.25 vfinal=-3.0 vdrain=-3.3  QSCV
save outf=devicepnp1.str

# extract device parameters......
extract init inf="mos1ex08_1.log"
extract name="pvt" (xintercept(maxslope(curve(abs(v."gate"),abs(i."drain")))) - abs(ave(v."drain"))/2.0)


extract init inf="mos1ex08_1.log"
extract name="pbeta" ((slope(maxslope(curve(abs(v."gate"),abs(i."drain")))) * (1.0/abs(ave(v."drain")))))

extract init inf="mos1ex08_1.log"
extract name="ptheta" ((max(abs(v."drain")) * $"pbeta")/max(abs(i."drain"))) - (1.0 / (max(abs(v."gate")) - ($"pvt")))




# plot results
tonyplot   devicepnp1.log -set c-v.set

quit

 

[Colbhaidh]

Your pmos device is shorted in the channel due to the sideways diffusion of boron Your structure needs to add spacers. Try this (remember I have a old verson of silvco so had to change some names around)

#PMOS
#Bulk: n-Si (1.5x1017 #/cm3)


go athena
#
# Set up a mesh suitable for a single MOSFET device....
#
line x loc=0.0 spac=0.001
line x loc=0.2 spac=0.005
line x loc=0.225 spac=0.01
#
line y loc=0.0 spac=0.001 
line y loc=0.01 spac=0.001
line y loc=0.1 spac=0.05
line y loc=0.35 spac=0.1

# Start off by defining silicon with 1.5e17 phos doping...
# Decrease the folowing space.mult parameter for a denser
# mesh and more accuracy...
init orientation=100 c.phos=1.5e17 space.mult=1
#
#Your pwell drive was redundant so removed
#
#screen oxide for nwell implant
deposit oxide thick=0.01

#N-well Implant
implant amorphous phos dose=8e11 energy=100 pears

#Anneal Implant
diffus temp=950 time=10 weto2 hcl=3

# well drive 
diffus time=20 temp=1200 nitro press=1

#
etch oxide all

#gate oxide
depo oxide thick=0.001
depo material=HfO2 thick=0.004 div=3 

#Extract a design parameter.....
extract name="gateox" thickness oxide mat.occno=1 x.val=0.005

#Deposit gate materal
depo material=AlSi thick=0.04
deposit photores thickness=0.01 div=3

etch photores p1.x=0.214 left
etch material=AlSi p1.x=0.214 left
etch material=HfO2 left p1.x=0.214
etch oxide p1.x=0.214 left
etch photores all

#Spacer formation
depo oxide thick=0.025
etch oxide thick = 0.030

#Implnd SD regions. Sideways diffusion beneath spacer creates LDD region
implant boron dose=1e18 energy=2

diffuse time=0.01 temp=900

#depo oxide thick=0.001
deposit material=AlSiCu thickness=0.045 div=8

etch material=AlSiCu thickness=0.045 right p1.x=0.150
etch material=AlSiCu thickness=0.045 left p1.x=0.050


# Extract design parameters

# extract final S/D Xj
extract name="nxj" xj silicon mat.occno=1 x.val=0.1 junc.occno=1

# extract the N++ regions sheet resistance
extract name="n++ sheet rho" sheet.res material="Silicon" mat.occno=1 x.val=0.05 region.occno=1

# extract the sheet rho under the spacer, of the LDD region
extract name="ldd sheet rho" sheet.res material="Silicon" \
	mat.occno=1 x.val=0.3 region.occno=1

# extract the surface conc under the channel.
extract name="chan surf conc" surf.conc impurity="Net Doping" \
	material="Silicon" mat.occno=1 x.val=0.45


# mirror the structure.....
structure mirror right

# Name the electrodes...

electrode name=gate x=0.225
electrode name=source x=0.10
electrode name=drain x=0.35

# output the structure
structure outfile=devicepnp0.str 

# plot it
tonyplot  devicepnp0.str