MOS Transistor Scalling (analog, digital, and mixed)

[jimjim2k]

Hi

What about MOS transistor re-sizing of a given working circuit with a technology (for example T1), when the designer decides to merge to another technology (for example T2)?



tnx

 

[mists]

hehe, I think there is not a general rule for this, you need to size it according you spec.

 

[Colbhaidh]

Shrinking an existing design on an existing process is much simpler. If you are running on a 0.35um process, it is often possible to shrink to say a 0.30um process (dumb shrink) to gain more devices on a wafer and reduce costs. The Fab or Foundry can usually do this if they already have experience or processes at much smaller geometries. This often requires little or no design intervention.
Howver to take a working design on say a stable 0.35um and convert it to say a 0.25um process unreleated to the 0.35um process is unlikely to work without considerable effort. The net list would require to be retested to the new Spice models and interconnect models and may require some selective resizing of transistors. So it is probably best to start from the schematic - recharacterise it to the new Spice models, adjust where required, then re-layout. This would better guarantee 1st pass success.

 

[sunking]

There are tools for changing.
In fact, low size can get low cost and high chara.

 

[hgdllt]

which tools?

 

[gl_master]

the tool?

 

[AdvaRes]

There are tools for changing.
In fact, low size can get low cost and high chara.

Please Explain.

 

[jecyhale]

Hi

What about MOS transistor re-sizing of a given working circuit with a technology (for example T1), when the designer decides to merge to another technology (for example T2)?



tnx

I think you can use the same size with new technology, then simulate it.
Then optimize it.

 

[forkschgrad]

full-custom?

 

[tuza2000]

i want to know how to optimize the circuit with new model , i think this is the point of the problem. wish someone give some advisize!!