MOS Threshold voltage

[rahulloveselectronics]

Hello,

I have a doubt regarding the physics involved for the threshold voltage of a mosfet.

If the Source-Bulk voltage is increased above zero (body effect), how would it physically lead to an increase in threshold voltage ?

My understanding was that (referring to an n-channel mosfet), the threshold voltage was physically the gate voltage which would make the minority carrier electron concentration in the surface/interface higher than the hole surface concentration, now when we increase the Vsb > 0, then the hole would be pushed deep into the bulk which means that the hole concentration in the surface is less now, now at a lower gate voltage cant the electron concentration exceed the surface hole concentration and hence the inversion layer occurs at a lower gate voltage.

Could you please correct my thoughts.......

 

[dgnani]

... the gate voltage which would make the minority carrier electron concentration in the surface/interface higher than the hole surface concentration...

I think at threshold (for an NMOS) is surface concentration of electrons equal bulk concentration of holes...

 

[rahulloveselectronics]

I think at threshold (for an NMOS) is surface concentration of electrons equal bulk concentration of holes...

But how exactly could it explain the increase in threshold voltage for the increment in the source-bulk voltage......................

 

[dgnani]

you said it yourself: increasing Vsb moves holes from the Si surface to the bulk...

 

[leo_o2]

I think theshold voltage is better to be define with Vgb instead of Vgs.
Actually body effect is used to reflect it.

 

[rahulloveselectronics]

you said it yourself: increasing Vsb moves holes from the Si surface to the bulk...

and if thats the case, as I presume that the Threshold voltage should reduce, is it right? Cos, the electron concentration in the surface would increase and hence the threshold happens at a lower value of the gate voltage (Vgb)..

Please correct me if I m wrong...

 

[VarunKumar89]

You said that the Vsb>0 for n-mos. Then the holes are pushed away and electrons (that are minority carriers in the p-substrate) are pulled towards substrate tap.
Hence more gate voltage needs to be applied to make a conducting path of electrons, thus there is increase in threshold level of mos.

For p-mos this happens in reverse flow
Thanks

 

[rahulloveselectronics]

You said that the Vsb>0 for n-mos. Then the holes are pushed away and electrons (that are minority carriers in the p-substrate) are pulled towards substrate tap.
Hence more gate voltage needs to be applied to make a conducting path of electrons, thus there is increase in threshold level of mos.

For p-mos this happens in reverse flow
Thanks

I believe that the conduction path in the inversion layer is caused due to the minority carriers (electrons) in the substrate (p-type), hence as the Vsb>0 brings in some electrons into the surface, therefore now only a lesser gate voltage is required to create the additional required electrons to make the inversion layer.