karthik225
Newbie level 1
Hello all,
I have implemented a MOS H bridge circuit to handle current upto 100uA as I need to bi-phasic current output.
When I change the direction of flow of current through the resistive load in the h bridge, I experience a very high glitch as shown in the picture below circled in red.
Could anyone suggest some solutions to reduce this glitch?
Thank you in advance.
PS: I am using high voltage transistors in 130nm CMOS technology.
I have implemented a MOS H bridge circuit to handle current upto 100uA as I need to bi-phasic current output.
When I change the direction of flow of current through the resistive load in the h bridge, I experience a very high glitch as shown in the picture below circled in red.
Could anyone suggest some solutions to reduce this glitch?
Thank you in advance.
PS: I am using high voltage transistors in 130nm CMOS technology.
moved to Analog IC Design & Layout [alexan_e]