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MOS H-Bridge problem with glitch

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karthik225

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Hello all,

I have implemented a MOS H bridge circuit to handle current upto 100uA as I need to bi-phasic current output.
When I change the direction of flow of current through the resistive load in the h bridge, I experience a very high glitch as shown in the picture below circled in red.
Could anyone suggest some solutions to reduce this glitch?
Thank you in advance.
PS: I am using high voltage transistors in 130nm CMOS technology.

hbridge.jpg
hbridge_1.jpg

moved to Analog IC Design & Layout [alexan_e]
 

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dick_freebird

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I see no attempt at break-before-make / anti-shoot-through timing,
which is a designed feature of most H-bridge driver products. I
think you want a non-overlap clock generator.
 
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threekingtiger

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Usually, people intentionally introduce some dead time for push-pull output stage or H bridge. Why not have a try? I hope it's helpful.
 

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