Thank you guys for your quick replies.
To be honest, what I want to do is a Band-gap Voltage Reference. First, I am starting to do the Differential Amplifier. The output voltage is 1.235V, the bias current is 1uA and the PSRR, from 1Hz to 1MHz, is 40dB. These are the main objective.
About the model that you refered to, BSIM3v3 model, I think that is that one that the cadence that I am using have. I will check that.
When I asked for the values of µn and Cox, of course that would be a estimation. But, even so, I'd like to do the math in order to know what to expect. More or less, and of course, to present some calculations.
The circuit that I am using to do the Folded Cascode Differential Amplifier is present in the CMOS Circuit Design, Layout, and Simulation book, in page 715. The Vbias3 is obtained by connecting the gate of two series NMOS transistors.
The Vbias1 and Vbias2 is obtained by two diode connected PMOS. There, exist a 1uA bias current.
For example, how do I have to think to know / what I need to count in order to calculate the Vbias3? I know the L, the ID, the Vov (=200mV) and the Cox and µn, so I do have everything to calculate the W -> W = (2 Id L) / (u Cox Vov^2). Now I ask, I am thinking well? Another doubt is related to those 2 transistors M5 (and above that one) and M6 (and the one above that).
I am really confused. Lost. Don't know how to start. Maybe drawing the circuit in cadence and them simulating until get the desired current in the branchs is easy, but I don't want to do that way.