Since you didn't post any of the definitions of the signals I'll just assume they are all std_logic_vectors.
Are you trying to write a software loop? You can't assign u in multiple passes through the loop using b(i) same goes for all the reset of the code you have in the generate.
Think about what you've written...
Your telling the compiler to create K3+1 copies of everything in the generate loop. So you have k3+1 copies of amulb that have all their inputs and outputs shorted to the same u and v1 same goes for add_sub.
You need to know what hardware you want and then write HDL that represents the hardware.