MOM Capacitor Simulation Problem

[AMSA84]

Hi guys,

I am trying to characterize (try to get the ESR) a MOM capacitor and I was using the SParameter from SPECTRE. After doing an SParameter analysis, I ask for the Real and Imaginary part of the capacitor and what I get is this:

**broken link removed**

I was wondering if the behavior of the Real part (supposed ESR) should be like what you can see in the picture above?

If it is not, how can I get the ESR value from the capacitor?

If it is, I can't understand that result...

Another question: When I tried to simulate in first place the capacitor, I was using the GND symbol from analogLib. I've connected the BULK to that same GND. When I did save there was an error that I can't remember now.

Because I couldn't simulate with that error, I removed the GND symbol and inserted a label with !gnd and then it worked fine.

Can someone tell me why I can't simulate using the GND symbol connected to the circuit? In the bottom plate of the capacitor (negative/reference) and in the BULK pin?

Regards.

 

[erikl]

Inject a unit current (1A) and run a simple ac analysis - on postLayout of course - and display a log-log plot of the capacitor voltage Vc. The horizontal start of the Vc=f(freq) curve at low frequencies shows the ESR (V ^= Ω).

The accuracy of the ESR calculation of course depends on the quality of the MOM's foundry model.

 

[AMSA84]

Hi erikl and thanks for the reply. I'll try that. However the model from my tech there is no series resistance...

By the way, I got the above results using the SP analysis.

Since the RF MOM cap model from my tech has the resistance modeled I was thinking to do the same simulation that I did before using this cap. erikl, in the RF MOM capacitor, there is a NW (I assume to be n-well) and a PSUB (p-substrate) terminal. I must connect those to gnd? I've connected those to gnd and I could simulate without any error. However I am just certifying that I am not doing anything wrong.

Regards.

 

[D.A.(Tony)Stewart]

It is possible the low freq simulation resonating effects are simulation resolution errors.

Can you do a Smith Reactance or Susceptance chart with constant current generator AC source?

Here is an interesting patent. https://www.freepatentsonline.com/7116544.pdf

ESR could be estimated by the track width, length and thickness , NO?

 

[AMSA84]

I can try. However, isn't the SP analysis enough?

 

[erikl]

Hi erikl and thanks for the reply. I'll try that. However the model from my tech there is no series resistance...

Then you can't get one from simulation, of course. Only in postLayout.

... in the RF MOM capacitor, there is a NW (I assume to be n-well) and a PSUB (p-substrate) terminal. I must connect those to gnd? I've connected those to gnd and I could simulate without any error. However I am just certifying that I am not doing anything wrong.

PSUB to gnd, NW to vdd (usually).

 

[AMSA84]

Okay, thanks for the reply.

erikl, regarding what you said about the postlayout, I thought that too. Taking into account that, do you think that should be better to do the simulation using the non-RF model (component) and do the postlayout simualtion, or using the RF model and then get the ESR value without needing to go for a postlayout simualtion?

 

[erikl]

Try the RF model first. Your result will be as good as the model is.

Extraction for post-layout analysis probably (hopefully) will extract the poly-to-contacts resistance and so should give you more realistic ESR values depending on the contacts' positions and distance.

 

[D.A.(Tony)Stewart]

Another way to test for ESR is to apply a square wave current such that the frequency is >100/(C*ESR) with a power limited to much less than the substrate can handle to avoid thermal rise and measure the peak to peak voltage in a burst in the target device for verification.

The capacitor will not have any time to charge up more than 1^% and all the voltage is due to ESR.

THe other is to make a kelvin bridge to match the impedance of ESR.

Then 1 milliohm resolution is possible using burst square wave to avoid thermal effects on resistance.

I'm not sure about avoiding measurement errors from mismatched impedance with ringing and your test measurement expertise but source and load impedances need to be low ESL for good results.