module generation and connection problem

[Fritzik]

hello
this is a module that should generate a BF_Switch by code (preperation for more then one)
i've tested the BF_Switch module and it works fine, but when i generated all of the wires and the module something got mixed up or something
here is the code:

module BF_Network(In_l,In_r,S_In_l,S_in_r,Clock,Out_l,Out_r,S_Out_l,S_Out_r);
	parameter SIZE = 2; // k == SIZE
	parameter ROWNUM = 0; // for i
	parameter HEIGHT = 0; // for j
	
	input [SIZE-1:0] In_l,In_r;
	input S_In_l,S_in_r,Clock;
	output [SIZE-1:0] Out_l,Out_r;
	output S_Out_l,S_Out_r;
	reg [SIZE-1:0] Out_l,Out_r;
	wire [SIZE-1:0] TEMP_Out_l,TEMP_Out_r;
	
	wire [1:0]IW_IOL[1:0];
	wire [1:0]IW_IOR[1:0];
	wire IW_SIOL[1:0];
	wire IW_SIOR[1:0];
	
	assign IW_IOL[0] = In_l; 
	assign IW_IOR[0] = In_r; 
	assign IW_SIOL[0] = `One; 
	assign IW_SIOR[0] = `One; 
	
	
	genvar j ;
	generate for (j=0; j<1; j=j+1) 
		begin:Build_Net
			//generate module BF_Network(In_l,In_r,S_In_l,S_in_r,Clock,Out_l,Out_r,S_Out_l,S_Out_r);
			BF_Switch #(SIZE,j) sw(IW_IOL[j],IW_IOR[j],IW_SIOL[j],IW_SIOR[j],Clock,IW_IOL[j+1],IW_IOR[j+1],IW_SIOL[j+1],IW_SIOR[j+1]);
		end
	endgenerate
	
	assign TEMP_Out_l = IW_IOL[1];
	assign TEMP_Out_r = IW_IOR[1];
	assign S_Out_l = IW_SIOL[1];
	assign S_Out_r = IW_SIOR[1];
	
	always @ (TEMP_Out_l or TEMP_Out_r) begin
		Out_l <= TEMP_Out_l;
		Out_r <= TEMP_Out_r;
	end
		
		
endmodule

for some reason i dont get any outputs OR - more strangly - only"Out_r" goes through and the others dont (i get zeros in simulation).
any thoughts or suggestions ?
plz help.

edit: still waiting - i realy need this help

 

[Fritzik]

please... i'm stuck real bad here

can anyone help ?