Modified booth algorithm [project help needed]

[gstekboy]

The below diagram is the parallel MAC structure. In parallel MAC both partial product addition and accumulation take place at same time.


The partial product summation + accumulation unit of above parallel mac is given below.


My problem : When I give input to multiplier as 00000101(5) and 00001000(8) what will be the values produced(P0[7:0],P1[7:0],P2[7:0],P3[7:0] And S0,S1,S2,S3 And N0,N1,N2,N3) that can be used as input of partial product generation + accumulation stage.

Normally by modified booth algorithm partial products generated will be of length 16 bit for 8 bit multiplication operation.Here partial products are of 10 bit.How it will give final correct answer?

The complete document is shared below.
https://www.mediafire.com/view/zoh8zuand88zkqx/05337888_2.pdf

Please share your ideas

 

[gstekboy]

Finally from literature I got that the booth algorithm used above is "Modified booth algorithm with reduced sign extension".