[SOLVED] ModelSim Waveform does not shown

[alvinhubert]

Hi! I have an irritating problem here. For my assignment, I tried simulating a fully dedicated architecture (FDA) code (from Quartus prime Lite Edition) in ModelSim SE-64 2020.4. I am not able to see the waveform on the wave window.

Here is my Datapath unit (DU) code.

module DU_6_3(clk, rst, ld1, ld2, ld3, ld4,SelR1, SelR2, SelR3, SelR4, SelM1, SelM2, SelA, a, b, c, d, e, R1, R2, R3, R4);
    input clk, rst, ld1, ld2, ld3, ld4, SelR3, SelR4, SelM1, SelM2, SelA;
    input [1:0]SelR1, SelR2;
    input [7:0]a, b, c, d, e;
    output reg [7:0]R1, R2, R3, R4;
    reg [7:0]Mul, Add1, Add2, Add3;  
   
    //Reg1
    always@(posedge clk, posedge rst)
        if(rst) R1 <= 0;
        else if(ld1)
            case(SelR1)
                2'b00: R1 <= a;
                2'b01: R1 <= Mul;
                2'b10: R1 <= Add1;
                2'b11: R1 <= 8'bxxxxxxxx;
            endcase
   
    //Reg2
    always@(posedge clk, posedge rst)
        if(rst) R2 <= 0;
        else if(ld2)
            case(SelR2)
                2'b00: R2 <= b;
                2'b01: R2 <= Add2;
                2'b10: R2 <= Mul;
                2'b11: R2 <= 8'bxxxxxxxx;
            endcase
   
    //Reg3
    always@(posedge clk, posedge rst)
        if(rst) R3 <= 0;
        else if(ld3)
            if(!SelR3) R3 <= c;
            else R3 <= e;
   
    //Reg4
    always@(posedge clk, posedge rst)
        if(rst) R4 <= 0;
        else if(ld4)
            if(!SelR4) R4 <= d;
            else R4 <= Add3;
   
    //Multiplier
    always@(SelM1, SelM2, R1, R2, R3, R4)
        case({SelM1, SelM2})
            2'b00: Mul = R1 * R4;
            2'b01: Mul = R2 * R4;
            2'b10: Mul = R1 * R3;
            2'b11: Mul = R2 * R2;
        endcase
   
    //Adder1
    always@(R1, R2, R3, SelA)
        if(SelA)
            Add1 <= R1 + R2;
        else
            Add1 <= R1 + R3;
   
    //Adder2
    always@(R1, R3)
        Add2 <= R1 + R3;
   
    //Adder3
    always@(R3, R4)
        Add3 <= R3 + R4;

     
endmodule

Here is my Controller unit (CU) code.

module CU_6_3(clk, rst, start, ld1, ld2, ld3, ld4, SelR1, SelR2, SelR3, SelR4, SelM1, SelM2, SelA, xdone, ydone, state);
    input clk, rst, start;
    output  ld1, ld2, ld3, ld4, SelR3, SelR4, SelM1, SelM2, SelA;
    output reg xdone, ydone;
    output [1:0] SelR1, SelR2;
    output reg [1:0]state;
    reg [1:0]next_state;
    reg [12:0] CV;
    parameter [2:0]S0=0, S1=1, S2=2, S3=3, S4=4;
   
    //state register
    always@(negedge clk, posedge rst)
        if(rst) state <= S0;
        else state <= next_state;
   
    //next state and CV logics
    always@(start or state)
        case(state)
            S0: begin CV = 13'h0000; xdone = 0; ydone = 0; if(start) next_state=S1; else next_state=S0;end
            S1: begin CV = 13'h1E18; xdone = 0; ydone = 0;next_state = S2;end
            S2: begin CV = 13'h1B21; xdone = 1; ydone = 0;next_state = S3;end
            S3: begin CV = 13'h1D44; xdone = 0; ydone = 1;next_state = S4;end
            S4: begin CV = 13'h1082; xdone = 0; ydone = 1;next_state = S0;end
            default:begin CV = 13'hxxxx; xdone = 0; ydone = 0;next_state = S0;end
        endcase
   
    // CV

    assign ld1 = CV[12];
    assign ld2 = CV[11];
    assign ld3 = CV[10];
    assign ld4 = CV[9];
    assign SelR1[1] = CV[8];
    assign SelR1[0] = CV[7];
    assign SelR2[1] = CV[6];
    assign SelR2[0] = CV[5];
    assign SelR3 = CV[4];
    assign SelR4 = CV[3];
    assign SelM1 = CV[2];
    assign SelM2 = CV[1];
    assign SelA = CV[0];
   
endmodule

Here is the verilog code for datapath unit (DU) and control unit (CU).

module DUCU_6_3(clk, rst, a, b, c, d, e, R1, R2, R3, R4, start, state, xdone, ydone);
    input clk, rst, start;
    input [7:0]a, b, c, d, e;
    output xdone, ydone;
    output [7:0]R1, R2, R3, R4;
    output [2:0]state;
    wire  ld1, ld2, ld3, ld4, SelR3, SelR4, SelM1, SelM2, SelA;
    wire [1:0] SelR1, SelR2;

    DU_6_3 Datapath(clk, rst, ld1, ld2, ld3, ld4, SelR1, SelR2, SelR3, SelR4, SelM1, SelM2, SelA, a, b, c, d, e, R1, R2, R3, R4);
    CU_6_3 Controller(clk, rst, start, ld1, ld2, ld3, ld4, SelR1, SelR2, SelR3, SelR4, SelM1, SelM2, SelA,xdone, ydone, state);                          
                               
endmodule

and here is the testbatch code for the code above.

`timescale 1ns/1ns
module DUCU_6_3_TB();
    reg clk, rst, start;
    reg [7:0]a, b, c, d, e;
    wire xdone, ydone;
    wire [7:0]R1, R2, R3, R4;
    wire [2:0]state;
   
    DUCU_6_3 DUT(clk, rst, start, a, b, c, d, e, R1, R2, R3, R4, state, xdone, ydone);
                                           
    initial begin
        clk=0;
        forever #10 clk=~clk;
        end
       
    initial begin
        #0    rst=1; a=1; b=2; c=3; d=4; e=5; start=0;
        #30 rst=0;
        #20 start=1;
        #20 start=0;
        #100 a=2; b=4; c=6; d=8; e=6;
        #20 start=1;
        #20 start=0;
        #100    $stop;
    end

endmodule

As you can see in the screenshot, the signals have been added to the wave window and the run icon clicked. Yet the waveforms show no data. Help is needed TQ!

 

[FvM]

You are simulating DUCU_6_3 rather than DUCU_6_3_TB. It has no stimuli at all, respectively no output.

To make DUCU_6_3_TB work, you need to fix the port order in DUCU_6_3 instantiation, a popular problem when using lazy connection method by ordered list.