fant123
Newbie level 5
verilog gate level simulation in modelsim
I'm using Modelsim 5.7, an I'm tryng to simulate a gate level netlist.
But if i use an implicit wire declaration es. or2 (siga,sigb,out); the simulator don't attach the net to the module output and I find always X.
But i if I check the module itself it behaves correctly.
Do anyone know if exist a directive for modelsim to compile thi sctructure?
I use the following commands:
vlog "library".v
vlog netlist.v
I'm using Modelsim 5.7, an I'm tryng to simulate a gate level netlist.
But if i use an implicit wire declaration es. or2 (siga,sigb,out); the simulator don't attach the net to the module output and I find always X.
But i if I check the module itself it behaves correctly.
Do anyone know if exist a directive for modelsim to compile thi sctructure?
I use the following commands:
vlog "library".v
vlog netlist.v