I'm still new to SystemVerilog, and I'm following the examples written in the book SystemVerilog for Design but Stuart Sutherland.
The first examples use struct for the data variables, and when I try to simulate using ModelSim, I can't use force. I tried forcing single elements, but it gives me the error:
Code:
Error: (vsim-3592) signal_force : Fields of user-defined types are not supported
and when I try to force the whole struct, I get this error:
Code:
# Cannot specify entire record value.
# ** Error: (vsim-4011) Invalid force value: {{32'h0054F321 32'h0043E210 8'h21}} 0.