VITALBehavior : process (ADR0_ipd, ADR1_ipd, ADR2_ipd)
variable O_zd : std_ulogic;
variable O_GlitchData : VitalGlitchDataType;
variable I_reg : std_logic_vector(2 downto 0);
begin
I_reg := To_StdLogicVector(ADR2_ipd & ADR1_ipd & ADR0_ipd);
if ((ADR2_ipd xor ADR1_ipd xor ADR0_ipd) = '1' or
(ADR2_ipd xor ADR1_ipd xor ADR0_ipd) = '0') then
O_zd := INIT_reg(SLV_TO_INT(I_reg));
else
O_zd := lut4_mux4 (('0' & '0' & lut4_mux4 ( INIT_reg(7 downto 4), I_reg(1 downto 0)) &
lut4_mux4 ( INIT_reg(3 downto 0), I_reg(1 downto 0))), ('0' & I_reg(2)));
end if;
VitalPathDelay01 (
OutSignal => O,
GlitchData => O_GlitchData,
OutSignalName => "O",
OutTemp => O_zd,
Paths => ( 0 => (ADR0_ipd'last_event, tpd_ADR0_O, true),
1 => (ADR1_ipd'last_event, tpd_ADR1_O, true),
2 => (ADR2_ipd'last_event, tpd_ADR2_O, true)),
Mode => VitalTransport,
Xon => Xon,
MsgOn => MsgOn,
MsgSeverity => warning);
end process;