post-synthesis modelsim error

[arbalez]

iteration limit reached modelsim

i got this modelsim problem after simulating a post-synthesis design from quartusII. why does this happen? i've tried to change the resolution to 1 ps, 1 ns, and even 1 us, but still the simulation doesn't run properly. is this got to do with the vhdl design code and its testbench? or other tool-related problem?

# ** Error: (vsim-3601) Iteration limit reached at time 0 us.
# ** Note: (vsim-3602) Delays were truncated during elaboration of the design.

thank you in advance.

 

[wadaye]

vsim-3601

Hi arbalez,

It's because your design that cause this warning, but this also simulation tool related.

It seems you use m0delsim, please try ncver1log or v_c_s if you have them.

 

[dBUGGER]

modelsim iteration limit reached

Hi,
I think the error comes because of your VHDL code. Check to see if you have used some loops in the VHDL code. This sometimes gives trouble when not initialized properly. Just check out.

Regards,

 

[archillios]

modelsim runtime options iteration limit

# ** Error: (vsim-3601) Iteration limit reached at time 0 us.

you may have a loop in your testbench with no delay control between successive passes.

so simulator keep runing inside the loop until max iteration limit is reached.

 

[arbalez]

zero-delay oscillation loop modelsim

thanks for replying.

this is my test bench. it's generated by QuartusII. i also have set higher "iterationlimit" (instead the default of 5000) in modelsim but i still got the same error. i'm not putting anything in the sensitivity list, so there shouldn't be any delay loop error. or the error lies in the design code itself?

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

ENTITY adpll_vhd_tst IS
END adpll_vhd_tst;
ARCHITECTURE adpll_arch OF adpll_vhd_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL t_sig_system_reset : STD_LOGIC;
SIGNAL t_sig_signal_in : STD_LOGIC;
SIGNAL t_sig_id_clk_in : STD_LOGIC;
SIGNAL t_sig_n_value : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL t_sig_k_clk_in : STD_LOGIC;
SIGNAL t_sig_k_modulus_bit : STD_LOGIC_VECTOR(3 downto 0);
SIGNAL t_sig_xor_out : STD_LOGIC;
SIGNAL t_sig_id_out : STD_LOGIC;
SIGNAL t_sig_lock_state : STD_LOGIC;
SIGNAL t_sig_k_counter_carry_outs : STD_LOGIC;
SIGNAL t_sig_k_counter_borrow_outs : STD_LOGIC;
COMPONENT adpll
	PORT (
	system_reset : in STD_LOGIC;
	signal_in : in STD_LOGIC;
	id_clk_in : in STD_LOGIC;
	n_value : in STD_LOGIC_VECTOR(3 downto 0);
	k_clk_in : in STD_LOGIC;
	k_modulus_bit : in STD_LOGIC_VECTOR(3 downto 0);
	xor_out : out STD_LOGIC;
	id_out : out STD_LOGIC;
	lock_state : out STD_LOGIC;
	k_counter_carry_outs : out STD_LOGIC;
	k_counter_borrow_outs : out STD_LOGIC	);
END COMPONENT;
BEGIN
	tb : adpll	PORT MAP (
-- list connections between master ports and signals
	system_reset => t_sig_system_reset,
	signal_in => t_sig_signal_in,
	id_clk_in => t_sig_id_clk_in,
	n_value => t_sig_n_value,
	k_clk_in => t_sig_k_clk_in,
	k_modulus_bit => t_sig_k_modulus_bit,
	xor_out => t_sig_xor_out,
	id_out => t_sig_id_out,
	lock_state => t_sig_lock_state,
	k_counter_carry_outs => t_sig_k_counter_carry_outs,
	k_counter_borrow_outs => t_sig_k_counter_borrow_outs
);
init : PROCESS                                               
-- variable declarations                                     
BEGIN                                                        
        -- code that executes only once   
        t_sig_n_value <= "1111"; 
        t_sig_k_modulus_bit <= "1000";    
        t_sig_system_reset <= '0';                     
WAIT;                                                       
END PROCESS init;                                           
always : PROCESS                                              
-- optional sensitivity list                                  
-- (        )                                                 
-- variable declarations                                      
BEGIN                                                         
        -- code executes for every event on sensitivity list
        t_sig_signal_in <= not t_sig_signal_in after 435 us;
        t_sig_k_clk_in <= not t_sig_k_clk_in after 13 us;
        t_sig_id_clk_in <= not t_sig_id_clk_in after 13 us;
WAIT;                                                        
END PROCESS always;                                          
END adpll_arch;

 

[aji_vlsi]

modelsim iteration limit reached

Hi,
Read their DOC. I found this in their doc:

Detecting infinite zero-delay loops
If a large number of deltas occur without advancing time, it is usually a symptom of an
infinite zero-delay loop in the design. In order to detect the presence of these loops,
ModelSim defines a limit, the “iteration limit", on the number of successive deltas that can
occur. When ModelSim reaches the iteration limit, it issues a warning message.
The iteration limit default value is 5000. If you receive an iteration limit warning, first
increase the iteration limit and try to continue simulation. You can set the iteration limit
from the Simulate > Runtime Options menu or by modifying the IterationLimit (UM-506)
variable in the modelsim.ini. See "Preference variables located in INI files" (UM-498) for
more information on modifying the modelsim.ini file.
If the problem persists, look for zero-delay loops. Run the simulation and look at the source
code when the error occurs. Use the step button to step through the code and see which
signals or variables are continuously oscillating. Two common causes are a loop that has
no exit, or a series of gates with zero delay where the outputs are connected back to the
inputs.

HTH
Ajeetha
www.noveldv.com

Added after 1 minutes:

Hi,
To add to my prev post - given that you are running post layout sim:

1. Do you have SDF annotated?
2. If not, did you set "delay_mode_unit" - that should solve most of such issues (Refer to MTI doc to see exact option)

Good Luck
Ajeetha
www.noveldv.com

 

[META60]

iteration limit reached at time

Dear all
i have these problems
# ** Error: (vsim-3601) Iteration limit reached at time 0 us.
# ** Note: (vsim-3602) Delays were truncated during elaboration of the design.
in VHDl code that it dose not have any delay_mode_unit option in VCOM

please guide me what i can do to solve this


thanks
best regards
M_taaassori