zermelo
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Modelsim compile error: t_sfixed function call "not a globally static expression"
Hi,
I get the following Modelsim error when compiling my design for simulation:
"# ** Error: tx_and_replica.vhd(362): Actual (function call "to_sfixed") for formal "i_x" is not a globally static expression."
The relevant code snippets are:
1) Port mapping: Line 362 is the s_tx_tmr conversion to signed fixed.
2) s_tx_tmr declaration:
3) Conflicting component entity:
I had this "globally static" Modelsim error before when using a case with the control signal length defined via generic. Now there are no generics involved in the conflictive type conversion.
What could be causing this?
zermelo
- - - Updated - - -
Hi,
Solved. It looks like Modelsim does not like signal conversion in port mappings.
Thanks
zermelo
Hi,
I get the following Modelsim error when compiling my design for simulation:
"# ** Error: tx_and_replica.vhd(362): Actual (function call "to_sfixed") for formal "i_x" is not a globally static expression."
The relevant code snippets are:
1) Port mapping: Line 362 is the s_tx_tmr conversion to signed fixed.
Code:
U_ITPL_TTL_HIGH: lin_itpl
Generic map
(G_COORD_DEC => s_step_low_freq'length,
G_COORD_FR => 0,
G_SLOPE_DEC => 1, -- We need the sign bit, the slope is negative!
G_SLOPE_FR => -s_step_slope'right)
Port map
(-- Reset & clock/clock en
i_rst => i_rst,
i_clk => i_clk,
i_conv => s_tx_cr_p_zc,
-- Inputs
i_slope => s_step_slope, -- decimal value
i_x => to_sfixed(std_logic_vector(s_tx_tmr),10,0), -- integer value
i_x1 => to_sfixed(0,10,0), -- integer value
i_y1 => s_step_low_freq,
-- Outputs
o_data_rdy => s_ttl_data_hi_rdy,
o_data => s_ttl_data_hi_fx);
2) s_tx_tmr declaration:
Code:
signal s_tx_tmr : unsigned(10 downto 0);
3) Conflicting component entity:
Code:
Library ieee_proposed;
library work;
use ieee.std_logic_1164.all ;
use ieee_proposed.fixed_pkg.all;
Entity lin_itpl is
Generic
(G_COORD_DEC : natural := 8; -- Applies to coordinates only
G_COORD_FR : natural := 2; -- Applies to coordinates only
G_SLOPE_DEC : natural := 1; -- Applies to slope only
G_SLOPE_FR : natural := 4); -- Applies to slope only
Port
(-- Reset & clock/clock en
i_rst : in std_logic;
i_clk : in std_logic;
i_conv : in std_logic;
-- Inputs
i_slope : in sfixed(G_SLOPE_DEC - 1 downto - G_SLOPE_FR);
i_x : in sfixed(G_COORD_DEC - 1 downto - G_COORD_FR);
i_x1 : in sfixed(G_COORD_DEC - 1 downto - G_COORD_FR);
i_y1 : in sfixed(G_COORD_DEC - 1 downto - G_COORD_FR);
-- Outputs
o_data_rdy : out std_logic;
o_data : out sfixed(G_COORD_DEC + G_SLOPE_DEC+1 downto -G_COORD_FR - G_SLOPE_FR));
end lin_itpl;
I had this "globally static" Modelsim error before when using a case with the control signal length defined via generic. Now there are no generics involved in the conflictive type conversion.
What could be causing this?
zermelo
- - - Updated - - -
Hi,
Solved. It looks like Modelsim does not like signal conversion in port mappings.
Thanks
zermelo