ModelSim and DO file :-(

[SphinX]

modelsim do file

Salam,

I'm FPGA Beginner so please can you help me in this problem


From Xilinx WebPack 6.2i i build a schematic (using Xilinx ECS)
The schematic is few logic gates connected together
I named the schematic file "Gates.sch"

And i wrote the next simple DO file "name.txt"

quit -sim
vsim Gates
view wave
add wave LowVolt
add wave Cord
add wave Temp
add wave Fan
add wave Alarm
force LowVolt 0, 1 10ns -r 20ns
force Cord 0, 1 20ns -r 40ns
force Temp 0, 1 40ns -r 80ns
run 80ns

Ok till now ?

Then from Xilinx ISE, I have lunched the ModelSim 6.0 SE

But ModelSim Give this

# do gates.ldo
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 6.0 Compiler 2004.08 Aug 19 2004
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package numeric_std
# ** Error: (vcom-19) Failed to access library 'unisim' at "unisim".
# No such file or directory. (errno = ENOENT)
# ** Error: D:/Modeltech_6.0/win32/vcom failed.
# Error in macro ./gates.ldo line 4# D:/Modeltech_6.0/win32/vcom failed.
# while executing
# "vcom -93 -explicit Gates.vhf"

There are two errors ? What are these errors mean ?

Then when i ran the do file (name.txt)

It give this

ModelSim> do name.txt

# OpenFile "Gates.sch"
# .wave
# ** Error: (vish-4008) Object 'LowVolt' not found.
# Error in macro ./name.txt line 33
# ** Error: (vish-4008) Object 'LowVolt' not found.#
# while executing
# "force LowVolt 0, 1 10ns -r 20ns"

And the wave windows is opened but it was empty.

I have checked the schematic, The name of IO Port 'LowVolt' is OK ?!

Any solution ?

 

[ugly_a]

modelsim .do file

Most likely your modelsim.ini file doesn't have read/write permission, or you don't have your unisim library compiled. Take a look at Answer record 10176 from Xilinx website and click on the links there to solve your problem.

Run some compxlib command that Xilinx website recommends, and you should be set to go.

 

[Charlie.za]

do file modelsim

Hi,

of course, you can have the unisim library no compiled.
Run the comand 'compxlib -h' at the modelsim prompt. It's easy to compile.
For the second question, I don't know. Usually I took that error when I was simulated a sinthesied design through a testbench file which hadn't the same signals of the original entity.

 

[masai_mara]

modelsim do

add this line "add wave *" after vsim command, now all the signals in your design are added to the wave window.
For the unisims error you need to have unsims complied into your work library or the lib name which unisim point to in the modesim.ini file.
The unisms for vhdl or verilog are found in the xilinx/vhdl/src or the xilinx/verilog/src folder.