I'm FPGA Beginner so please can you help me in this problem
From Xilinx WebPack 6.2i i build a schematic (using Xilinx ECS)
The schematic is few logic gates connected together
I named the schematic file "Gates.sch"
And i wrote the next simple DO file "name.txt"
quit -sim
vsim Gates
view wave
add wave LowVolt
add wave Cord
add wave Temp
add wave Fan
add wave Alarm
force LowVolt 0, 1 10ns -r 20ns
force Cord 0, 1 20ns -r 40ns
force Temp 0, 1 40ns -r 80ns
run 80ns
Most likely your modelsim.ini file doesn't have read/write permission, or you don't have your unisim library compiled. Take a look at Answer record 10176 from Xilinx website and click on the links there to solve your problem.
Run some compxlib command that Xilinx website recommends, and you should be set to go.
of course, you can have the unisim library no compiled.
Run the comand 'compxlib -h' at the modelsim prompt. It's easy to compile.
For the second question, I don't know. Usually I took that error when I was simulated a sinthesied design through a testbench file which hadn't the same signals of the original entity.
add this line "add wave *" after vsim command, now all the signals in your design are added to the wave window.
For the unisims error you need to have unsims complied into your work library or the lib name which unisim point to in the modesim.ini file.
The unisms for vhdl or verilog are found in the xilinx/vhdl/src or the xilinx/verilog/src folder.