after using both i actually perfer modelsim.. one of the biggest reason is the zoom function in the waveform window.. so much easier to use.. im lazy so it works out
for interface, ms is better. but for big size design, vendor support etc, you must choice ldv.
some module(ip) write with protected, i don't think ms can treat it, just ldv.
for module, you could choice ms. at chip level, ldv or vcs is better.
I would prefer to LDV base on the two reasons.
First, LDV is better for mixed language (verilog and vhdl) simulation.
Second, the simulation rate especially for gate-level simulation of LDV is faster than the Modelsim's.
LDV and Debussy are always what i use in my RTL and netlist simulation and debugy.
LDV can handle larger design than modelsim.
of course modelsim is convenient when you deal with small modules
for interface, ms is better. but for big size design, vendor support etc, you must choice ldv.
some module(ip) write with protected, i don't think ms can treat it, just ldv.
for module, you could choice ms. at chip level, ldv or vcs is better.
But modelsim can handle this too,but if the vendor dont use modelsim , you cant use modelsim when encypted by ldv whereas you can;t use ldv when encypted by modelsim!!!just so so
i just know ldv is logical design and verification tool suite ,so where to display its design abililty,but ms is just a verification tool ,is it right?
But modelsim can handle this too,but if the vendor dont use modelsim , you cant use modelsim when encypted by ldv whereas you can;t use ldv when encypted by modelsim!!!just so so
i just know ldv is logical design and verification tool suite ,so where to display its design abililty,but ms is just a verification tool ,is it right?