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really? i think ms is good for mixed language.galant said:LDV is better for mixed language (verilog and vhdl) simulation.
But modelsim can handle this too,but if the vendor dont use modelsim , you cant use modelsim when encypted by ldv whereas you can;t use ldv when encypted by modelsim!!!just so soz81203 said:for interface, ms is better. but for big size design, vendor support etc, you must choice ldv.
some module(ip) write with protected, i don't think ms can treat it, just ldv.
for module, you could choice ms. at chip level, ldv or vcs is better.
kermit said:But modelsim can handle this too,but if the vendor dont use modelsim , you cant use modelsim when encypted by ldv whereas you can;t use ldv when encypted by modelsim!!!just so so
sxqzj said:i just know ldv is logical design and verification tool suite ,so where to display its design abililty,but ms is just a verification tool ,is it right?