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Modelling parameterised models with verilog

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funjoke

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Model a memory with synchoronous read and write operations that meet the following specifications.

-The memory has an address bus width of ADDR_SIZE
-The memory has a bidirectional data bus with the width DATA_SIZE.
-The memory chip is enabled using an enable signal.When the chip is disabled ,the data bus should be freed.
-A single signal that is used to read and write data to the memory array.When the signal is LOW,data is written to the memory array.When HIGH,data is read from the memory array.However,when not reading from memory,the data bus should be freed.

You are required to use parameter and localpram.


Answer:
module ram_syn_b1_0
#(parameter ADDR_SIZE=6
DATA_SIZE=4)
(inout [DATA_SIZE-1:0] iop_data,
input [ADDR_SIZE-1:0] ip_addr,
input ip_chip_en,
input ip_read_write_n);

//Memory depth is 2**ADDR_SIZE.
localpram MEM_DEPTH=1<<ADDR_SIZE;

//Create a memory array.
reg[DATA_SIZE-1:0]r_mem[0:MEM_DEPTH-1];

//Create logic for reading from memory array
//Read from memory.
always@(ip_read_write_n,ip_chip_en,ip_addr)
if(ip_chip_en&&ip_read_write_n)
iop_data=r_mem[ip_addr];
else
iop_data={DATA_SIZE{1'bz}};

if (ip_chip_en)
if(ip_read_write_n)
iop_data=r_mem[ip_addr];
else
iop_data={DATA_SIZE{1'bz}};
else
iop_data={DATA_SIZE{1'bz}};

//Create logic for writing to the memory array
always@(ip_read_write_n,ip_chip_en,ip_addr,iop_data)
if(ip_chip_en&&!ip_read_write_n)
r_mem[ip_addr]=iop_data;

end module

can help me check whether my answer is correct ?thanks
 

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