Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
I have forgotten what set does, I think it sets the value of the flop to 1? The following should work.
Reset part should be easy. Attach the Q pin of the flop to the A pin of a two input AND gate. Pin B on the AND gate is your reset. If you attach the output the AND gate to the A pin of a two input OR gate, then the B pin of the OR gate can be your Set pin.
What shahal mentions wont work as the effect of set or reset has to stay even after set/ reset is gone till the next data comes in. One way to do this for a synchronous reset/set is to do what shahal mentioned (OR for set and AND for reset) but do it with the D pin (input data) so that when CLK comes in and when SET/RESET is present either a zero or one would get clocked in instead of the actual data. There is no way though to modify it in such way you can set/reset asynchronously. Hope it helps.
-Ranga
I am not sure I understand why this wont work, now that I think of it. If one input of an AND gate is set to zero. the output will always be zero regardless of what comes into the other input from the Q pin of the flop. Similar situation for the OR gatye also if one of the input is set to 1.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
