LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY bcd_count IS
PORT(Clock : IN STD_LOGIC;
Clear,E : IN STD_LOGIC;
bcd0,bcd1 : out STD_LOGIC_VECTOR(3 DOWNTO 0));
END bcd_count;
ARCHITECTURE logicfunc OF bcd_count IS
signal bcd0_tmp,bcd1_tmp,b1_latch,b0_latch: STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(Clock)
BEGIN
IF Clock'EVENT AND Clock ='1' THEN
IF Clear = '1' THEN bcd1 <= "0000";
bcd0 <= "0000";
bcd0_tmp<="0000";
bcd1_tmp<="0000";
ELSIF E = '1' THEN
IF bcd0_tmp = "1001" THEN bcd0_tmp <= "0000";
IF bcd1_tmp = "1001" THEN bcd1_tmp <= "0000";
ELSE bcd1_tmp <= b1_latch + '1';
END IF;
ELSE bcd0_tmp <= b0_latch + '1';
END IF;
END IF;
bcd0<=bcd0_tmp;
bcd1<=bcd1_tmp;
END IF;
END PROCESS;
b0_latch<=bcd0_tmp;
b1_latch<=bcd1_tmp;
END logicfunc;