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MOD10 Counter-count sequence help

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TKruger

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Hi Guys
I have designed a BCD-counter that gets displayed on 2x 7 segment displays.
Each display counts 9 and resets, i.e the least significant display starts off at 0 and when it reaches 9,it resets to 0 and it increments the most significant display to a one and so on.
But the counting sequence of the least significant is not counting sequentialy, meaning 0,1,2...9. It is counting weird:1,5,7,8,9.

Now my question is: "Can the clock signal influence the counting sequence???"
"Do you need a 50% duty cycle on your clock signal??"

Here is my code attached - "mod10"
 

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TrickyDicky

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more likely the clear signal isnt synchronised, so the registers are not cleared properly.
 

TKruger

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Hi TrickyDicky
How can i make the clear synchronized??
Can you possibly provide me with a program?

It will greately be appreciated.
Thank you.
 

corin.otesteanu

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I simulated your program - timing simulation (after synthesis and routing) and it works just fine.
The duty cycle shouldn't matter. Problems may occur only if your clock isn't stable, or if the duty cycle varies a lot. Even so you should see a normal sequence (0,1 ,2) but the time is stays on each number would be different.
What frequency does the clock have? Because you increment your counter on each clock cycle, that would mean the numbers on your display change each clock cycle (and if it is above 100Hz you should see all segments dim on the least significant bit display).
The only things I can advise you is not to use buffer for the output signal since it complicates the logic inside the fpga and avoid using recurrent statements as bcd0<=bcd0 + 1.
Here's my version of the program:
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;

ENTITY bcd_count IS
PORT(Clock	: IN STD_LOGIC;
	 Clear,E   : IN STD_LOGIC;
	 bcd0,bcd1	: out STD_LOGIC_VECTOR(3 DOWNTO 0));
END bcd_count;

ARCHITECTURE logicfunc OF bcd_count IS	  
	signal bcd0_tmp,bcd1_tmp,b1_latch,b0_latch: STD_LOGIC_VECTOR(3 DOWNTO 0); 
BEGIN
	PROCESS(Clock)

	 BEGIN
		   IF Clock'EVENT AND Clock ='1' THEN 
		      IF Clear = '1' THEN bcd1 <= "0000";
			 bcd0 <= "0000";	 
			 bcd0_tmp<="0000";
			 bcd1_tmp<="0000";
		      ELSIF E = '1' THEN
		         IF bcd0_tmp = "1001" THEN bcd0_tmp <= "0000";
		           IF bcd1_tmp = "1001" THEN bcd1_tmp <= "0000";
		           ELSE bcd1_tmp <= b1_latch + '1';
		           END IF;
		         ELSE bcd0_tmp <= b0_latch + '1';
		         END IF;
		      END IF;
			  bcd0<=bcd0_tmp;
			  bcd1<=bcd1_tmp;
		   END IF;
	 END PROCESS;
	 
  b0_latch<=bcd0_tmp;
  b1_latch<=bcd1_tmp;
END logicfunc;
Anyway, I think your version of the code should also work.
 

TKruger

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Hi Corin, how are you?
My oscillator is a 555 timer running at 1Hz with more or less a 50% duty cycle.

I will give your code a try and report back to you if it works.
Thank you very much for your help and the code you provided me, I greately appreciate it.
Regards
Tiaan
 

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