Dick_FreeBird,
Thanks for your message.
The only way of getting a handle of the L as you said, is to do EM simulation of the passives and interconnect you feel are part of critical nodes in your circuit topology, correct ?
I mean you cannot - just not time for all that - just EM simulate all the interconnect between stages and all the interconnect at the inputs and outputs, unless they are critical - correct ? Too time consuming I would imagine.
Say I lay out one stage of a 3 stage MMWave amplifier - I extract the transistors and the interconnect. I am extracting one stage at a time to see the effect on the performance than using the extraction in simulation with the rest of non layout extracted stages to see how the performance changes. I deem the input node of my stage to be a critical node. If I EM simulate just the input node and associated passives, then use that to see the effect on performance, is that "more valid" than the RC extraction itself ? Do you understand my question ? Is their a purpose to doing an RC extraction and then EM simulation ?
Thank you.