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MMD division value load maximum delay

NikosTS

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Hello everyone,
Suppose we have a Fractional-N frequency synthesizer employing an MMD + 3rd order MASH loop. If we want to divide by the fractional value 100.XX ( where XX = fractional value ) , the MASH will instruct the MMD to divide by values between 97 - 104.
My question is , which is the maximum delay for a new division value to be loaded from MASH to the divider?
At first glance, you would say it should be 1 period of VCO frequenct in order not to lose a single period between the 2 divison values. However because of the architecture of MMD , as I understand, there is some extra time that you can still load a new value without dividing wrongly.
If Tvco is the output period of the VCO, could we quantify this maximum delay in terms of VCO periods? E.g , max delay = 10*Tvco?

If i wasnt clear enough, please tell me so I can explain it better

Thank you advance
 

pancho_hideboo

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Simply you can not understand things correctly.
Clock of MASH is a divided clock output not constant.
 

NikosTS

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Yeap i get it , i dont understand anything at all. Can we move on please?
 

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