Mixed Simulation of Design (VHDL and Verilog)

[Mirzaaur]

instance verilog in vhdl

Dear all,

I need to simulate my design with another design which was done already in verilog. module in Verilog will communicate with the Design in VHDL.

I did simulation of my Design in VHDL using a test bench, but for practical reasons I need to used the other design in same test.

HOW TO USE A DESIGN(VERILOG) IN A VHDL DESIGN SIMULATION??

PLEASE ADVISE, ANY TIPS, ANY KIND OF LITRATURE??

thanks in advance,

mirza

 

[semiconductorman]

verilog & vhdl mixed simulation

Most simulators now support mixed mode simultaion.
You can instantiate a VHDL module inside verilog or vice versa . When compling the design make sure you compile it in the right order. i,e, if VHDL module is an instance in verilog , compile all your vhdl files and then your verilog files. After that just compile as usaul.

 

[anilkumarv]

vhdl instance in verilog

Use mixed language simulators, for example synopsys has a tool by name VCS MX in which codes of both verilog and VHDL can be compiled and sumulated together (refer its pdfs for the commands)

 

[go4sandesh_vsn]

vcs vhdl verilog mixed simulation

whichever simulation tool u r using...make sure if it supports mixed HDLs (nowadays most of them do).....n just follow its related documentation.....

particularly for Modelsim, u can follow its "modelsim_user.pdf" file ...it has an entire chapter dedicated to mixed lang simulation....

hope it helps