Mixed signal verification question with Nanosim + VCS

[blueagate]

set_node_thresh

I am debugging a mixed signal design by using Nanosim + VCS.

The analog circuit is described in spice and the digital circuit is

described in Verilog.

A clock named A2DCLK is generated by analog circuit and feed to digital circuit.

While A2DCLK rise from 0 to 3.3v, the corresponding digital signal is rise from 0 to unknown and then to 1. Because the state of unknown take place, the signals which triggered at the rise edge of A2DCLK in RTL do not change.


always @ (posedge A2DCLK or negedge nRST)
begin
if(~nRST)
f_count[7:0] <=8'h00;
else
f_count[7:0] <= f_count[7:0] + 1;
end


After reset, f_count holding in 0.

Is there a solution?

I have tried the set_node_thresh in Nanosim configure file, but did not work. Then, I added +2state compile direction on VCS complie script, it did not work too.

By the way, does somneone know how to add a sin/cos stimulus in Verilog testbench?

 

[adap]

Shouldn't the counter count in the Verilog code? I mean :

else
f_count[7:0] <= f_count[7:0] + 8'h1;

 

[blueagate]

The counter in Verilog HDL did not count because there was an unknown state in A2DCLK.

 

[akp494]

Hello Blugate

In your case I asume that the clock signal from Analog block is coming properly. But the moment it goes to digital domain you are seeing an unknown state for some time on the clock signal.

So you may have to check the ADC(Analog to digital converter) models the tool is picking and placing on the clock signal. The threshold voltages specified in ADC models are very importtant. Generally these models are in Verilog-A or Verilog-AMS. These are predefined by the tool. We can alter the threshold voltages in these models according to our need.