mixed signal ESD protection

[whlinfei]

Hi All,

I am designing a Class D amplifier with three power domains,namely power, digital and analog.

Now I am at the stage of drawing the layout for pads and esd protections.

I see normally there is ESD Vdd and ESD ground for connection of input esd diodes.
But that will degrade the noise performance and power dissipation of the chip.

I was wondering if there is any guideline for mixed signal ESD protections since a common esd Vdd/ Vss path is not an option.

Thank you in advance.

Best Regards,
whlinfei

 

[love_analog]

That should not degrade noise.

Yes leakage will be there. What is your leakage limit?

You can create your own ESD cells but it will be difficult to get it validated by foundry. Remember you cannot simulate ESD breakdowns and transistor melting because of that.

 

[dick_freebird]

Switching circuits are "interesting" because the ground
bounce can be greater than a forward diode drop, allowing
that to get into places it shouldn't (like your analog loop, Vref
might not be helped by charge pumping).

You may have to stack diodes to allow yourself some room
for some amount of bounce, because you won't get to zero.
Quantifying the likely amount of it on a well-designed board
in the end application, might be good to try (though not to
entirely believe).

You can simulate ESD breakdowns if you bother to take the
data and fit it up. I do it. But maybe your foundry doesn't.
Mine neither, which is why I bother. You can design ESD
protection pretty well if you go at it methodically.

 

[whlinfei]

Hi,

I am using IBM 130nm process. There are some standard cells like ESD HBM diode, CDM resistors.

I cannot change the configuration and layer and all that. What I can vary is the size and connections.

Regarding the limit, the smaller the better. There is no strict specification for that as it's university project.

What I want to know is the ESD protection plans if there is more than one power domain.

Thanks.
Best Regards,
whlinfei

Added after 7 minutes:

Switching circuits are "interesting" because the ground
bounce can be greater than a forward diode drop, allowing
that to get into places it shouldn't (like your analog loop, Vref
might not be helped by charge pumping).

I limited the bounce by using more than one pin and added in internal capacitors. That is not the problem for my design.

The concern I have is that even with diode strings as you mentioned, noises from digital and power domains can still couple into the analog domain through parasitic capacitance of the ESD diodes, if there is a common ESD Vdd and ESD ground.

I read somewhere that bus-to-bus esd can be used in mixed signal design esd, but I am not sure which one is more reliable and noise free ?
The common ESD Vdd and ground OR bus-to-bus ESD ?

Thank you.
Best Regards,
Linfei

 

[mikersia]

For mixed signal and multiple supply domain from my view poin is preferable to use ESD design method with "Common Discharge Line" (CDL). CDL is typically GNDs domains connected between each other by cross coupled diodes. VDDs lines are not connected with each other. Each power domain shall have effective ESD power clamps to it's ground, better to have a distributed clamps.