Kicchan
Member level 3
I have a mixed signal ASIC with one full custom section designed in Cadence Virtuoso and another one designed in Verilog to be implemented with the standard cell library of my technology.
Now I must put the two things together for backend.
I have already generated the lef file for the full custom stage but I don't know if the synthesis must be either perfomed at the top level (with the semi custom not structural yet and recalling the full custom) or for the semi custom alone (and then putting the two blocks together during place and route).
Can anyone provide tutorials/material about this procedure? I have read the "Digital VLSI chip design with cadence and synopsis CAD tools" book which is pretty useful but it doesn't mention how to proceed in situations like this (it gives examples only with the ccar tool but not with Synopsis).
Thanks in advance
Now I must put the two things together for backend.
I have already generated the lef file for the full custom stage but I don't know if the synthesis must be either perfomed at the top level (with the semi custom not structural yet and recalling the full custom) or for the semi custom alone (and then putting the two blocks together during place and route).
Can anyone provide tutorials/material about this procedure? I have read the "Digital VLSI chip design with cadence and synopsis CAD tools" book which is pretty useful but it doesn't mention how to proceed in situations like this (it gives examples only with the ccar tool but not with Synopsis).
Thanks in advance