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minimum width of a metal for handling a given current in CMOS technology

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Nov 4, 2009
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How to determine the minimum width of metal layer for handling a given current in a specific CMOS technology?

If I want to handle 2mA, how to determine the width of metal?

It depends to height of metal layer which is determined by process. All numbers (max current per µm) for given metal layer You have in process documentation.

Thank you Dominik Przyborowski
1 mA/um assumption is valid even for short channel technologies, too? for example for 90nm or 45 nm technologies?

That number is "roughly right" for metal layers in the 8kA
thickness range but thickness is a (the) key factor. This
also includes via / contact step coverage if the via fill is
same species (likely, though, vias are tungsten plugs in
a CMP interconnect stack, which bring their own
electromigration issues).

Many technologies offer thicker, upper metal layers
which can be used to advantage for power routing. At
the cost of routing density.

In any case you're on the hook for foundry current density
rules, at signoff.

Example:For a power device I just calculated:

Minimum metal requirements:
Metal1-4 Current capacity at 125c is 0.67mA/µ
Metal5 Current capacity at 125c is 4.02mA/µ

Total Width = 11,000 um Total Current = 150mA Drains/Sources= 31 (D/S)

Current per D/S requirements

150mA/31 drains or sources = 4.84mA per D/S

Minimum Metal 1 width required is 4.84mA/0.67mA = 7.22µm


Layering the Metal 1 and 2 vertically together halves the resistance and doubles the metal current capability of the device.
Metal 1 and 2 Combined
0.67mA/µ X 2 =1.34mA per 1µm

(So remember Current per D/S requirements 150mA/31 drains or sources = 4.84mA per D/S)

Minimum Metal 1 & 2

4.84mA / 1.34mA = 3.61µm of metal required per D/S

Using Metal 3 layer next reduces the current requirements by 2 as half the device will be connected to metal 3 and metal 4 and the metal is stacked upto metal 4.

Minimum Metal 1 & 2 required = 3.61µm per D/S will reduce by x2 = 1.805µm per finger ( Recommend 2µm)


Layering the Metal 3 and 4 horizontal
Metal 3 and 4 Combined
0.67mA/µ X 2 =1.34mA per 1µm

Metal 3 & 4 estimated 6 straps of 30µm ( 3 per D/S) Based on width of device

Each strap would take 1.34mA X 30µm = 40 mA x 3 = 120mA

Whist this does not meet 150mA target it would be ok as long as the metal 5 is sufficient with at least two straps splitting the current up over the device


Layering the Metal 5
Metal 5
Metal5 Current capacity at 125c is 4.02mA per 1 µm

120mA / 150mA -0.8 = 80%

As long as the metal 5 connects to the Straps within 80% of the device current density will be met.

2x 35um per D/S x 4.02mA = 281mA Capability

For 150mA a minimum of 37.31 µm of metal 5 is required.


After all that the designer recalculated and changed the Max current to 100mA!
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