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Minimum MIM cap problem

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sibanda

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Hello,

Im designing a 12-bit SAR ADC where I need to choose a unit capacitor based on matching requirements. It is desirable to keep the unit capacitor small down to 5 fF so that settling time requirements can also be met. However, the MIM Cap pcell in the PDK does not allow a capacitor value of less than 26.7fF (W=5um, L=5um). Having series combinations of capacitors will increase the area consumption significantly. Wondering why they don't allow a smaller capacitor because my calculations show that a capacitor much smaller than 26.7 fF can meet the matching requirements of the design. Can anyone shed light on this?

The PDK documentation reports a mismatch of 5nm for the MIM capacitor. Density is 1fF/um^2.

Regards,
Sibanda
 

erikl

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If you're sure you can do with such a small unit cap (think of routing parasitics!), I'd copy the existing pCell (with all its views) to a different name and reduce its size up to our needs (probably (2.24 µm)2).
 

sibanda

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Hi erikl,

thanks for the reply. Actually I'm curious as to why this is the lower limit on the capacitor size.

Here's how I calculate the error:

Error in 0.1fF cap = (5nm x 5nm)/0.1um^2 = 250ppm
this corresponds to about -72dB which is the dynamic range of a 12 bit adc
so basically I can have a unit capacitor as low as 0.1fF

Do you see a problem with this approach?

Thanks,
Sibanda
 

dick_freebird

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MIM cap bounds are set by what somebody believed designers
would want for tolerances, and the fab's ability to hold them.
MIM cut is often through a very thick upper level ILD that
will make for poor etch control. If you had a 1um thick
dielectric, a 0.1um per side etch tolerance would not be
unreasonable and that would be about 4% dimension error
at a 5um drawn cut, and a 8% area (capacitance) tolerance
neglecting entirely the MIM dielectric thickness tolerance.
Now go to 2.4um and you would see 17% area tolerance
at that same 0.1um litho tolerance. What you do not know,
and what PCM statistics will probably fail to show, is unit to
unit etch uniformity.

Using a unit capacitor that approaches the semiconductor
and interconnect parasitic capacitances will leave you a lot
of additional variability (esp. w/ common mode voltage that
modulates the FET drain parasitics). Your charge division
ratios on which CDACs work, need to be consistent across
the working range. Otherwise you'd go and use the more
area efficient and probably better matched MOS caps. But
you don't, for good reasons.
 

Dominik Przyborowski

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The minimum size of MIMCAP depends to design rules. Check in the process documentation minimum width/length of MIMCAP metal layers and try to make a flattened cell for unit capacitor which passes DRC.
 

t4_v

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As Dominik Przyborowski pointed out the minimum size of MIMCAP (its W and L) are set by foundry. It is the same as with any element that you are using in your technology: NMOS, PMOS, resistors, inductors etc.

As erikl pointed out remember that parasitics can add to the value of your capacitor.

You didn't tell that there is a must to use MIM capacitors. Thus, remember that you can always use different capacitors as poly-poly or MOS cap or others that your foundry provides. Maybe you'll find something that meets 5 fF criteria.
 

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