Minimum Capacitor value in 0.18um

[Usman Hai]

Hi guys,
Just wondering what could be the minimum value of capacitor we can fabricate on chip. It must be limited by the mismatch. Someone told me its around 25fF. Is this assumption correct?

 

[tshankar501]

It mostly depends on the application you are working on. If your circuit can withstand mismatch then you can layout a capacitor of much lower value. You also need to worry about the kT/C noise. Usually the mismatch would be normal distribution and could also be approximated as delta(C)/C proportional to 1/sqrt(C). So the lower the value of the capacitance, the higher the mismatch.

 

[RFDE]

dpeneding on the technology , you can obtain smaller values by using MOS cap's , i read a paper by TI about all digital PLL & there technology enables them to have a step in capacitance down to atto's range!!

 

[Usman Hai]

Thanks guys,
I am working on a pipelined ADC, and assuming it is of 10 bits. We scale the capacitor along the pipelined stages and this scaling is limited by the mismatch in the capacitor. So what could be the minimum value of capacitor we can built in this case. I know that the relative change in capacitor sizes must be less than half LSB.
Regards,

 

[tshankar501]

In a pipeline ADC, you may or may not want to scale down the capacitors. You could have the same capacitor size and still could implement the RSD logic. Anyway coming to capacitor values, from whatever I have read, I would stick to 100f for better matching. Somebody who had first hand experience on pipeline adc on 0.18u could throw some light on this. Also plz let us know of what type of caps are you dealing with, whether it is metal-metal or poly-poly or any other?