#### Analogworld

##### Member level 1

**tsmc 0.2um process**

Hi all,

I was wondering how do I determine the minimum gate length L for the transistor to use in Spice simulation (0.18um or 0.2um)?

I heard that since the lambda=0.1um for 0.18um, so we have to use 0.2um(2*lambda) as the minimum length. However, I also look at the MOSIS website, they said lambda=0.09 for the SCN6M_DEEP model. The site link is the following:

***broken link removed***

So, could anyone help me to clarify what is minimum gate length that I should/can use when simulating the transistors? Any help would be greatly appreciated.