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Min. gate length use in spice simulation for 0.18um TSMC MM

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Analogworld

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tsmc 0.2um process

Hi all,

I was wondering how do I determine the minimum gate length L for the transistor to use in Spice simulation (0.18um or 0.2um)?

I heard that since the lambda=0.1um for 0.18um, so we have to use 0.2um(2*lambda) as the minimum length. However, I also look at the MOSIS website, they said lambda=0.09 for the SCN6M_DEEP model. The site link is the following:

http://www.mosis.org/cgi-bin/cgiwrap/umosis/swp/params/tsmc-018/t58f_mm_non_epi_thk-params.txt

So, could anyone help me to clarify what is minimum gate length that I should/can use when simulating the transistors? Any help would be greatly appreciated.
 

pkalavakuru

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0.18um spice parameters

Hi


Min gate lenght is nothing but in which Technology ur desiging

for ex: 0.18u ur min gate length is .18u

0.2u technolgy .ur Min gate lenght is .2u

Have a nice time

Added after 3 minutes:

Hi


Min gate lenght is nothing but in which Technology ur desiging

for ex: 0.18u ur min gate length is .18u

0.2u technolgy .ur Min gate lenght is .2u

Have a nice time
 

Analogworld

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0.18um gate length

Hi,

Thanks for the reply. But it seems the min. gate length that I can use in spice simulation is not only based on the technology process. I have been seen a lot peoples that using 0.2um as the min. length in 0.18um process. I just wondering why is this.
 

pkalavakuru

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tsmc 0.18u spice.txt

Hi

Generally designers keep their channel length above thier minimum Gate length to avoid channel length modulation ,especially while designing current mirrors...e.t.c

Theoritically/practically u can take 0.18u(basend on ur technology) r whatever as gate length..u should be careful while dimensioning ur length of transistor..as per i said when ur designing Current mirrors...Differential pair..something like that ..

with regards
 

Chethan

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channel length modulation 0.18 um

If you are designing a standard cell in 0.18u process then ur min length is 0.18u. But as u r using MM process then i guess u r designing an analog or mixed signal block. in that case take the length of ur transistors atleast twice or thrice of ur min length(0.18um).
 

dumbfrog

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tsmc 0.18 um length

use minimum for digital
and 4X for current reference
and 2X~3X for analog
 
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