MIM capacitance parasitics

[alexs]

Hi,
I am designing layout of fully differential opamp using UMC 0.18 technology. For compensation purposes my op amp contains MIM 8pF capacitance. After layout RC parasitics extraction (I used Assura for this purpose) I have found that parasitic capacitances for both net connected to given MIM capacitor is about 4pF (given value decrease opamp GBW). I have found that this value is only due to the MIM capacitor large area. Is so large value (50% from initial value) of parasitics is okay? Any suggestion how can decrease parasitics or I need simply account this capacitance during desing (decrease initial capacitance in schematic).

Thanks in advance for all replies!!!

Alexey

 

[JoannesPaulus]

Are you sure you are extracting the parasitic capacitance correctly? 4pF seems to be rather large...
At any rate, if your extraction is correct, you should absolutely include the parasitic capacitors in your schematics and adjust the design to account for it!

I hope it helps!

 

[oermens]

are you sure you're looking at the instances of pcapacitor? if your foundry models have the same symbol maybe you're mixing them up. look in the netlist.

 

[alexs]

I also agree that this value is too large.

I check the value of parasitic capacitance for the nets using Virtuoso all nets table (from Parasitics menu).
If I decrease the value of MIM capacitor (therefore the area and pcapacitance) I see the pcapacitace is decreased in given table.

Is this correct way for checking pcapacitance?
Can you suggest any other way for checking.

Alexey.

 

[monya11]

Extractions can sometimes be missleading. 4p is way too large capacitance. You can check it by extracting and by old good hand calculations with the ruler and some number from the process.

 

[sat]

It might happen the MIM cap is double counted - make sure that is not the case.
By saying double counted I mean - it was already extracted during LVs netlisting, then RC extraction tool again extracted the cap fully - because of lack of blocking statements [maybe]

Check-A
----------
check the QRC/RCX log file.
There will be a section showing [maybe Forking: ] capgen -[several_options_especially_check_for_blocking_options] - you must see the MIMcap_device_recognition_layer and a comma separated list of layers that is blocked from cap extraction. If you cannot find so, definitely a double counting has taken place.

1. check every blocking statement.
2. be careful, the device being blocked may have a name *not* same as device/cellName, it is it's corresponding device recognition layer name [you can find the link by taking a look inside the extraction rules used during LVS].

Check-B [ you can do Check-B, b4 Check-A ]
------------
Another way to check - check your LVS layout netlist - check for total value of all of canonical caps for the net, where one or,maybe couple of MIMcaps are instantiated , now re-run RC extraction with a simple spice netlist out with decoupled cap only extraction [this time you may skip R extraction], if extracted netlist, total cap on the net, is more than 2x[LVS value] - it is perhaps double counted during extraction.

 

[alexs]

Hi sat,
I agree with you that such large value of parasitic capacitor is due to counting of MIM capacitor during extraction.

I have performed check that you recommend but it is difficult to me to interpret the results:

Check A:
I find the capgen part in RCX log file but cannot find any layer blockage rules
this is all that I find:

capgen Capgen results will be written to directory: /home/asevasty/work1/nmos_mm_test
Forking: /home/asevasty/cadence/assura317/tools/assura/bin/32bit/capgen -techdir /home/asevasty/umc_pdk/cds_pdk/RuleDecks/Assura/./LPE -lvs /home/asevasty/work1/nmos_mm_test.xcn -p2lvs /home/asevasty/umc_pdk/cds_pdk/RuleDecks/Assura/./LPE/p2lvsfile -length_units meters -p ply,Allgates,dif -cap_unit 1 -mos_diff_ap_nw /home/asevasty/work1/nmos_mm_test
*INFO* at "RCXspice": the automatic substrate resolution feature will become default in AV3.1.7. This feature can be activated in AV316_USR2 by the environment variable QRC_AUTO_SUBSTRATE_RESOLUTION=Y

Check B:
I created simple circuit containing one nmos and one mim. In the LVS netlist there is 2 exact two devices (nmos and mim).

After the C only extraction I have netlist with 3 devices (nmos mim pcapacitor).

lib cell view total
UMC_18_CMOS MIMCAPS_MM symbol 1
UMC_18_CMOS N_18_MM symbol 1
UMC_18_CMOS pcapacitor symbol 1



In the generated parasitics netlist I see one coupled pcap beetween net which is connected to my original mim (original mim value 8p - coupled pcap value about 4p).

Any suggestion that is wrong?

Alexey